Reviewed-by: Rodrigo Vivi <rodrigo.vivi at gmail.com>
On Wed, Mar 21, 2012 at 10:10 PM, Eugeni Dodonov
<eugeni.dodonov at intel.com> wrote:
> Those have different functionality on Haswell architecture, so let's
> trigger a warning message when we are going through a path we should not
> go into on Haswell.
>
> This patch is here for make debugging and log tracing easier, it should
> go away in the future, we we'll stop hitting those code paths.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
> ?drivers/gpu/drm/i915/intel_display.c | ? 59 +++++++++++++++++++++++++++-------
> ?1 file changed, 47 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index a37e0b7..10b92e8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -847,9 +847,16 @@ static void assert_fdi_tx(struct drm_i915_private *dev_priv,
> ? ? ? ?u32 val;
> ? ? ? ?bool cur_state;
>
> - ? ? ? reg = FDI_TX_CTL(pipe);
> - ? ? ? val = I915_READ(reg);
> - ? ? ? cur_state = !!(val & FDI_TX_ENABLE);
> + ? ? ? if (IS_HASWELL(dev_priv->dev)) {
> + ? ? ? ? ? ? ? DRM_ERROR("Attempting to check FDI_TX_CTL on Haswell, using DDI instead\n");
> + ? ? ? ? ? ? ? reg = DDI_FUNC_CTL(pipe);
> + ? ? ? ? ? ? ? val = I915_READ(reg);
> + ? ? ? ? ? ? ? cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
> + ? ? ? } else {
> + ? ? ? ? ? ? ? reg = FDI_TX_CTL(pipe);
> + ? ? ? ? ? ? ? val = I915_READ(reg);
> + ? ? ? ? ? ? ? cur_state = !!(val & FDI_TX_ENABLE);
> + ? ? ? }
> ? ? ? ?WARN(cur_state != state,
> ? ? ? ? ? ? "FDI TX state assertion failure (expected %s, current %s)\n",
> ? ? ? ? ? ? state_string(state), state_string(cur_state));
> @@ -864,9 +871,14 @@ static void assert_fdi_rx(struct drm_i915_private *dev_priv,
> ? ? ? ?u32 val;
> ? ? ? ?bool cur_state;
>
> - ? ? ? reg = FDI_RX_CTL(pipe);
> - ? ? ? val = I915_READ(reg);
> - ? ? ? cur_state = !!(val & FDI_RX_ENABLE);
> + ? ? ? if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + ? ? ? ? ? ? ? ? ? ? ? DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
> + ? ? ? ? ? ? ? ? ? ? ? return;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? reg = FDI_RX_CTL(pipe);
> + ? ? ? ? ? ? ? val = I915_READ(reg);
> + ? ? ? ? ? ? ? cur_state = !!(val & FDI_RX_ENABLE);
> + ? ? ? }
> ? ? ? ?WARN(cur_state != state,
> ? ? ? ? ? ? "FDI RX state assertion failure (expected %s, current %s)\n",
> ? ? ? ? ? ? state_string(state), state_string(cur_state));
> @@ -884,6 +896,11 @@ static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
> ? ? ? ?if (dev_priv->info->gen == 5)
> ? ? ? ? ? ? ? ?return;
>
> + ? ? ? if (IS_HASWELL(dev_priv->dev)) {
> + ? ? ? ? ? ? ? DRM_ERROR("Attempting to check FDI_TX_PLL on Haswell, aborting\n");
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> ? ? ? ?reg = FDI_TX_CTL(pipe);
> ? ? ? ?val = I915_READ(reg);
> ? ? ? ?WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
> @@ -895,6 +912,10 @@ static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
> ? ? ? ?int reg;
> ? ? ? ?u32 val;
>
> + ? ? ? if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + ? ? ? ? ? ? ? DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> ? ? ? ?reg = FDI_RX_CTL(pipe);
> ? ? ? ?val = I915_READ(reg);
> ? ? ? ?WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
> @@ -1000,6 +1021,11 @@ static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
> ? ? ? ?u32 val;
> ? ? ? ?bool enabled;
>
> + ? ? ? if (HAS_PCH_LPT(dev_priv->dev)) {
> + ? ? ? ? ? ? ? DRM_ERROR("LPT does not has PCH refclk, skipping check\n");
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> +
> ? ? ? ?val = I915_READ(PCH_DREF_CONTROL);
> ? ? ? ?enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
> ? ? ? ? ? ? ? ? ? ? ? ? ? ?DREF_SUPERSPREAD_SOURCE_MASK));
> @@ -1323,6 +1349,10 @@ static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
> ? ? ? ?assert_fdi_tx_enabled(dev_priv, pipe);
> ? ? ? ?assert_fdi_rx_enabled(dev_priv, pipe);
>
> + ? ? ? if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
> + ? ? ? ? ? ? ? DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
> + ? ? ? ? ? ? ? return;
> + ? ? ? }
> ? ? ? ?reg = TRANSCONF(pipe);
> ? ? ? ?val = I915_READ(reg);
> ? ? ? ?pipeconf_val = I915_READ(PIPECONF(pipe));
> @@ -3308,13 +3338,18 @@ static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
> ? ? ? ?udelay(200);
>
> ? ? ? ?/* Enable CPU FDI TX PLL, always on for Ironlake */
> - ? ? ? reg = FDI_TX_CTL(pipe);
> - ? ? ? temp = I915_READ(reg);
> - ? ? ? if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> - ? ? ? ? ? ? ? I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
> + ? ? ? if (IS_HASWELL(dev)) {
> + ? ? ? ? ? ? ? DRM_ERROR("Skipping enablement of FDI_TX_PLL on Haswell\n");
> + ? ? ? ? ? ? ? return;
> + ? ? ? } else {
> + ? ? ? ? ? ? ? reg = FDI_TX_CTL(pipe);
> + ? ? ? ? ? ? ? temp = I915_READ(reg);
> + ? ? ? ? ? ? ? if ((temp & FDI_TX_PLL_ENABLE) == 0) {
> + ? ? ? ? ? ? ? ? ? ? ? I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
>
> - ? ? ? ? ? ? ? POSTING_READ(reg);
> - ? ? ? ? ? ? ? udelay(100);
> + ? ? ? ? ? ? ? ? ? ? ? POSTING_READ(reg);
> + ? ? ? ? ? ? ? ? ? ? ? udelay(100);
> + ? ? ? ? ? ? ? }
> ? ? ? ?}
> ?}
>
> --
> 1.7.9.2
>
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--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br
GPG: 0x905BE242 @ wwwkeys.pgp.net
