On Wed, Mar 21, 2012 at 12:48:34PM -0700, Jesse Barnes wrote:
> On VLV we need to flush the TLBs of the Gunit when updating PTEs. We
> could put this off until we've written a whole block of entries, but we
> don't currently have a nice place to put that.
>
> Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org>
> ---
> drivers/char/agp/intel-agp.h | 1 +
> drivers/char/agp/intel-gtt.c | 19 ++++++++++++++++++-
> 2 files changed, 19 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
> index 5da67f1..4c0854d 100644
> --- a/drivers/char/agp/intel-agp.h
> +++ b/drivers/char/agp/intel-agp.h
> @@ -96,6 +96,7 @@
> #define G4x_GMCH_SIZE_VT_2M (G4x_GMCH_SIZE_2M | G4x_GMCH_SIZE_VT_EN)
>
> #define GFX_FLSH_CNTL 0x2170 /* 915+ */
> +#define GFX_FLSH_CNTL_VLV 0x0x101008
>
> #define I810_DRAM_CTL 0x3000
> #define I810_DRAM_ROW_0 0x00000001
> diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
> index 19b6486..8d5bef3 100644
> --- a/drivers/char/agp/intel-gtt.c
> +++ b/drivers/char/agp/intel-gtt.c
> @@ -1179,6 +1179,23 @@ static void gen6_write_entry(dma_addr_t addr, unsigned int entry,
> writel(addr | pte_flags, intel_private.gtt + entry);
> }
>
> +static void valleyview_write_entry(dma_addr_t addr, unsigned int entry,
> + unsigned int flags)
> +{
> + unsigned int type_mask = flags & ~AGP_USER_CACHED_MEMORY_GFDT;
> + unsigned int gfdt = flags & AGP_USER_CACHED_MEMORY_GFDT;
> + u32 pte_flags;
> +
> + if (type_mask == AGP_USER_MEMORY)
> + pte_flags = GEN6_PTE_UNCACHED | I810_PTE_VALID;
> +
> + /* gen6 has bit11-4 for physical addr bit39-32 */
> + addr |= (addr >> 28) & 0xff0;
> + writel(addr | pte_flags, intel_private.gtt + entry);
> +
> + writel(1, intel_private.registers + GFX_FLUSH_CNTL_VLV);
> +}
> +
> static void gen6_cleanup(void)
> {
> }
> @@ -1350,7 +1367,7 @@ static const struct intel_gtt_driver sandybridge_gtt_driver = {
> .gen = 6,
> .setup = i9xx_setup,
> .cleanup = gen6_cleanup,
> - .write_entry = gen6_write_entry,
> + .write_entry = valleyview_write_entry,
> .dma_mask_size = 40,
> .check_flags = gen6_check_flags,
> .chipset_flush = i9xx_chipset_flush,
By now I'm pretty sure you want to add a new vlv gtt driver - this won't
work so well on snb. One thing on my todo that's been on it for way too
long is to move all the gtt crap to drm/i915/i915_gem_gtt.c for gen6+
(where we never supported ums). This could make the vlv code in here a bit
.impler, but I'm ok with adding more cruft in intel-gtt.c, too.
-Daniel
--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
