Since ValleyView is a gen7 chip but doesn't have the same turbo interface. Signed-off-by: Jesse Barnes <jbarnes at virtuousgeek.org> --- drivers/gpu/drm/i915/i915_drv.c | 4 ++++ drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/intel_display.c | 2 +- 3 files changed, 7 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 48fc5ab..6c92ded 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -220,6 +220,7 @@ static const struct intel_device_info intel_sandybridge_d_info = { .has_bsd_ring = 1, .has_blt_ring = 1, .has_llc = 1, + .has_turbo = 1, }; static const struct intel_device_info intel_sandybridge_m_info = { @@ -229,6 +230,7 @@ static const struct intel_device_info intel_sandybridge_m_info = { .has_bsd_ring = 1, .has_blt_ring = 1, .has_llc = 1, + .has_turbo = 1, }; static const struct intel_device_info intel_ivybridge_d_info = { @@ -237,6 +239,7 @@ static const struct intel_device_info intel_ivybridge_d_info = { .has_bsd_ring = 1, .has_blt_ring = 1, .has_llc = 1, + .has_turbo = 1, }; static const struct intel_device_info intel_ivybridge_m_info = { @@ -246,6 +249,7 @@ static const struct intel_device_info intel_ivybridge_m_info = { .has_bsd_ring = 1, .has_blt_ring = 1, .has_llc = 1, + .has_turbo = 1, }; static const struct intel_device_info intel_valleyview_m_info = { diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 178a955..024f574 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -266,6 +266,7 @@ struct intel_device_info { u8 has_bsd_ring:1; u8 has_blt_ring:1; u8 has_llc:1; + u8 has_turbo:1; }; #define I915_PPGTT_PD_ENTRIES 512 @@ -1025,6 +1026,7 @@ struct drm_i915_file_private { #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring) #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring) #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc) +#define HAS_TURBO(dev) (INTEL_INFO(dev)->has_turbo) #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws) #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 8668d38..dc0ef17 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -9715,7 +9715,7 @@ void intel_modeset_init(struct drm_device *dev) intel_init_emon(dev); } - if (IS_GEN6(dev) || IS_GEN7(dev)) { + if (HAS_TURBO(dev)) { gen6_enable_rps(dev_priv); gen6_update_ring_freq(dev_priv); } -- 1.7.5.4