On Tue, Mar 05, 2019 at 01:46:55PM -0800, Anusha wrote:
> From: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
>
> Comet Lake is a Intel Processor containing Gen9
> Intel HD Graphics. This patch adds the initial set of
> PCI IDs. Comet Lake comes off of Coffee Lake - adding
> the IDs to Coffee Lake ID list.
>
> More support and features will be in the patches that follow.
>
> v2: Split IDs according to GT. (Rodrigo)
>
> Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> Cc: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
> ---
> drivers/gpu/drm/i915/i915_pci.c | 2 ++
> include/drm/i915_pciids.h | 31 ++++++++++++++++++++++++++++++-
> 2 files changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index a9211c370cd1..63ca4ffcad8a 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -723,6 +723,8 @@ static const struct pci_device_id pciidlist[] = {
> INTEL_WHL_U_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_AML_CFL_GT2_IDS(&intel_coffeelake_gt2_info),
> INTEL_WHL_U_GT3_IDS(&intel_coffeelake_gt3_info),
> + INTEL_CML_GT1_IDS(&intel_coffeelake_gt1_info),
> + INTEL_CML_GT2_IDS(&intel_coffeelake_gt2_info),
I prefer the order that you added here, but this is not the currently
order in use. worth to sort WHL/AML with per-platform instead of per-gt?
> INTEL_CNL_IDS(&intel_cannonlake_info),
> INTEL_ICL_11_IDS(&intel_icelake_11_info),
> {0, 0, 0}
> diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
> index d2fad7b0fcf6..e9ed75ac8252 100644
> --- a/include/drm/i915_pciids.h
> +++ b/include/drm/i915_pciids.h
> @@ -373,6 +373,34 @@
> #define INTEL_AML_CFL_GT2_IDS(info) \
> INTEL_VGA_DEVICE(0x87CA, info)
>
> +/* CML GT1 */
> +#define INTEL_CML_GT1_IDS(info) \
> + INTEL_VGA_DEVICE(0x9BA1, info), \
> + INTEL_VGA_DEVICE(0x9BAA, info), \
> + INTEL_VGA_DEVICE(0x9BAB, info), \
> + INTEL_VGA_DEVICE(0x9BAC, info), \
> + INTEL_VGA_DEVICE(0x9BA0, info), \
> + INTEL_VGA_DEVICE(0x9BA5, info), \
> + INTEL_VGA_DEVICE(0x9BA8, info), \
> + INTEL_VGA_DEVICE(0x9BA4, info), \
> + INTEL_VGA_DEVICE(0x9BA2, info)
> +
> +/* CML GT2 */
> +#define INTEL_CML_GT2_IDS(info) \
> + INTEL_VGA_DEVICE(0x9BC1, info), \
> + INTEL_VGA_DEVICE(0x9BCA, info), \
> + INTEL_VGA_DEVICE(0x9BCB, info), \
> + INTEL_VGA_DEVICE(0x9BCC, info), \
> + INTEL_VGA_DEVICE(0x9BC0, info), \
> + INTEL_VGA_DEVICE(0x9BC5, info), \
> + INTEL_VGA_DEVICE(0x9BC8, info), \
> + INTEL_VGA_DEVICE(0x9BC4, info), \
> + INTEL_VGA_DEVICE(0x9BC2, info)
would you believe me if I tell you the table changed again? :P
> +
> +#define INTEL_CML_IDS(info) \
> + INTEL_CML_GT1_IDS(info), \
> + INTEL_CML_GT2_IDS(info)
> +
> #define INTEL_KBL_IDS(info) \
> INTEL_KBL_GT1_IDS(info), \
> INTEL_KBL_GT2_IDS(info), \
> @@ -436,7 +464,8 @@
> INTEL_WHL_U_GT1_IDS(info), \
> INTEL_WHL_U_GT2_IDS(info), \
> INTEL_WHL_U_GT3_IDS(info), \
> - INTEL_AML_CFL_GT2_IDS(info)
> + INTEL_AML_CFL_GT2_IDS(info), \
> + INTEL_CML_IDS(info)
>
> /* CNL */
> #define INTEL_CNL_IDS(info) \
> --
> 2.21.0
>
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