On 06/04/2012 06:18 AM, Daniel Vetter wrote: > Empirical evidence suggests that we need to: On at least one ivb > machine when running the hangman i-g-t test, the rings don't properly > initialize properly - the RING_START registers seems to be stuck at > all zeros. > > Holding forcewake around this register init sequences makes chip reset > reliable again. Note that this is not the first such issue: > > commit f01db988ef6f6c70a6cc36ee71e4a98a68901229 > Author: Sean Paul<seanpaul at chromium.org> > Date: Fri Mar 16 12:43:22 2012 -0400 > > drm/i915: Add wait_for in init_ring_common > > added delay loops to make RING_START and RING_CTL initialization > reliable on the blt ring at boot-up. So I guess it won't hurt if we do > this unconditionally for all force_wake needing gpus. > > To avoid copy&pasting of the HAS_FORCE_WAKE check I've added a new > intel_info bit for that. > > v2: Fixup missing commas in static struct and properly handling the > error case in init_ring_common, both noticed by Jani Nikula. > > Cc: stable at vger.kernel.org > Reported-by: Yang Guang<guang.a.yang at intel.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=50522 > Signed-Off-by: Daniel Vetter<daniel.vetter at ffwll.ch> The new .has_forcewake looks nice! Just one very tiny bikeshed below :). Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com> > @@ -285,6 +285,7 @@ struct intel_device_info { > u8 is_ivybridge:1; > u8 is_valleyview:1; > u8 has_pch_split:1; > + u8 has_force_wake:1; > u8 is_haswell:1; > u8 has_fbc:1; > u8 has_pipe_cxsr:1; While you are on it, maybe it would make sense to move is_haswell up, so all the 'is_*' and 'has_*' flags would stay together? It is partly may fault though, due to the has_pch_split which ended up in wrong place, but as you are touching those fields anyway, perhaps we could rectify it for the future? :) Eugeni
