On Fri, Jun 29, 2012 at 04:03:33PM -0300, Paulo Zanoni wrote:
> From: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> IMHO, that code really belongs to intel_dp_set_link_train. The caller
> functions are also big, so now they'll be a little bit easier to read.
I've gotten rather confused with this patch until I've figure out what
you're actually doing. I think it'd be nice to explain what you mean by
"common code" exactly. What about adding:
- Change set_link_train to also do the right thing when disabling link
training so that it can be used in the complete_link_train function.
- Don adjust the DP_CTL value in the caller, instead select the right
bitmask for the desired training pattern according to dp_train_pat.
Yours, Daniel
>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> ---
> drivers/gpu/drm/i915/intel_dp.c | 77 ++++++++++++++++++++++++---------------
> 1 file changed, 47 insertions(+), 30 deletions(-)
>
> We'll add even more code to intel_dp_set_link_train on Haswell.
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 76a7080..e315f73 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1672,6 +1672,41 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> struct drm_i915_private *dev_priv = dev->dev_private;
> int ret;
>
> + if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
> + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + case DP_TRAINING_PATTERN_DISABLE:
> + dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
> + break;
> + case DP_TRAINING_PATTERN_1:
> + dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
> + break;
> + case DP_TRAINING_PATTERN_2:
> + dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
> + break;
> + case DP_TRAINING_PATTERN_3:
> + DRM_ERROR("DP training pattern 3 not supported\n");
> + dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
> + break;
> + }
> +
> + } else {
> + switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
> + case DP_TRAINING_PATTERN_DISABLE:
> + dp_reg_value |= DP_LINK_TRAIN_OFF;
> + break;
> + case DP_TRAINING_PATTERN_1:
> + dp_reg_value |= DP_LINK_TRAIN_PAT_1;
> + break;
> + case DP_TRAINING_PATTERN_2:
> + dp_reg_value |= DP_LINK_TRAIN_PAT_2;
> + break;
> + case DP_TRAINING_PATTERN_3:
> + DRM_ERROR("DP training pattern 3 not supported\n");
> + dp_reg_value |= DP_LINK_TRAIN_PAT_2;
> + break;
> + }
> + }
> +
> I915_WRITE(intel_dp->output_reg, dp_reg_value);
> POSTING_READ(intel_dp->output_reg);
>
> @@ -1679,12 +1714,15 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
> DP_TRAINING_PATTERN_SET,
> dp_train_pat);
>
> - ret = intel_dp_aux_native_write(intel_dp,
> - DP_TRAINING_LANE0_SET,
> - intel_dp->train_set,
> - intel_dp->lane_count);
> - if (ret != intel_dp->lane_count)
> - return false;
> + if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
> + DP_TRAINING_PATTERN_DISABLE) {
> + ret = intel_dp_aux_native_write(intel_dp,
> + DP_TRAINING_LANE0_SET,
> + intel_dp->train_set,
> + intel_dp->lane_count);
> + if (ret != intel_dp->lane_count)
> + return false;
> + }
>
> return true;
> }
> @@ -1700,7 +1738,6 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> uint8_t voltage;
> bool clock_recovery = false;
> int voltage_tries, loop_tries;
> - u32 reg;
> uint32_t DP = intel_dp->DP;
>
> /*
> @@ -1748,12 +1785,7 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
> }
>
> - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
> - reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
> - else
> - reg = DP | DP_LINK_TRAIN_PAT_1;
> -
> - if (!intel_dp_set_link_train(intel_dp, reg,
> + if (!intel_dp_set_link_train(intel_dp, DP,
> DP_TRAINING_PATTERN_1 |
> DP_LINK_SCRAMBLING_DISABLE))
> break;
> @@ -1808,10 +1840,8 @@ static void
> intel_dp_complete_link_train(struct intel_dp *intel_dp)
> {
> struct drm_device *dev = intel_dp->base.base.dev;
> - struct drm_i915_private *dev_priv = dev->dev_private;
> bool channel_eq = false;
> int tries, cr_tries;
> - u32 reg;
> uint32_t DP = intel_dp->DP;
>
> /* channel equalization */
> @@ -1840,13 +1870,8 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
> }
>
> - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
> - reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
> - else
> - reg = DP | DP_LINK_TRAIN_PAT_2;
> -
> /* channel eq pattern */
> - if (!intel_dp_set_link_train(intel_dp, reg,
> + if (!intel_dp_set_link_train(intel_dp, DP,
> DP_TRAINING_PATTERN_2 |
> DP_LINK_SCRAMBLING_DISABLE))
> break;
> @@ -1881,15 +1906,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> ++tries;
> }
>
> - if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp)))
> - reg = DP | DP_LINK_TRAIN_OFF_CPT;
> - else
> - reg = DP | DP_LINK_TRAIN_OFF;
> -
> - I915_WRITE(intel_dp->output_reg, reg);
> - POSTING_READ(intel_dp->output_reg);
> - intel_dp_aux_native_write_1(intel_dp,
> - DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
> + intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
> }
>
> static void
> --
> 1.7.10.2
>
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--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
