Instead of using several GT_GEN(), let's pass the range to
GT_GEN_RANGE(). By code inspection these were the ranges deemed
necessary for spatch:
@@
expression e;
@@
(
- GT_GEN(e, 3) || GT_GEN(e, 2)
+ GT_GEN_RANGE(e, 2, 3)
|
- GT_GEN(e, 3) || GT_GEN(e, 4)
+ GT_GEN_RANGE(e, 3, 4)
|
- GT_GEN(e, 5) || GT_GEN(e, 6)
+ GT_GEN_RANGE(e, 5, 6)
|
- GT_GEN(e, 6) || GT_GEN(e, 7)
+ GT_GEN_RANGE(e, 6, 7)
|
- GT_GEN(e, 7) || GT_GEN(e, 8)
+ GT_GEN_RANGE(e, 7, 8)
|
- GT_GEN(e, 8) || GT_GEN(e, 9)
+ GT_GEN_RANGE(e, 8, 9)
|
- GT_GEN(e, 10) || GT_GEN(e, 9)
+ GT_GEN_RANGE(e, 9, 10)
|
- GT_GEN(e, 9) || GT_GEN(e, 10)
+ GT_GEN_RANGE(e, 9, 10)
)
Signed-off-by: Lucas De Marchi <lucas.demarchi@xxxxxxxxx>
---
drivers/gpu/drm/i915/gvt/gtt.c | 2 +-
drivers/gpu/drm/i915/i915_debugfs.c | 6 +++---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/intel_crt.c | 2 +-
drivers/gpu/drm/i915/intel_device_info.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_engine_cs.c | 2 +-
drivers/gpu/drm/i915/intel_fifo_underrun.c | 2 +-
drivers/gpu/drm/i915/intel_pipe_crc.c | 4 ++--
drivers/gpu/drm/i915/intel_uncore.c | 6 +++---
11 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index bc79c154391d..692de9b9779b 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -1025,7 +1025,7 @@ static bool vgpu_ips_enabled(struct intel_vgpu *vgpu)
{
struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
- if (GT_GEN(dev_priv, 9) || GT_GEN(dev_priv, 10)) {
+ if (GT_GEN_RANGE(dev_priv, 9, 10)) {
u32 ips = vgpu_vreg_t(vgpu, GEN8_GAMW_ECO_DEV_RW_IA) &
GAMW_ECO_ENABLE_64K_IPS_FIELD;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ec26076aaecc..9ffcf0be0589 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2030,7 +2030,7 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
swizzle_string(dev_priv->mm.bit_6_swizzle_y));
- if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4)) {
+ if (GT_GEN_RANGE(dev_priv, 3, 4)) {
seq_printf(m, "DDC = 0x%08x\n",
I915_READ(DCC));
seq_printf(m, "DDC2 = 0x%08x\n",
@@ -4262,7 +4262,7 @@ i915_cache_sharing_get(void *data, u64 *val)
struct drm_i915_private *dev_priv = data;
u32 snpcr;
- if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)))
+ if (!(GT_GEN_RANGE(dev_priv, 6, 7)))
return -ENODEV;
intel_runtime_pm_get(dev_priv);
@@ -4282,7 +4282,7 @@ i915_cache_sharing_set(void *data, u64 val)
struct drm_i915_private *dev_priv = data;
u32 snpcr;
- if (!(GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)))
+ if (!(GT_GEN_RANGE(dev_priv, 6, 7)))
return -ENODEV;
if (val > 3)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 0de8ce65053d..e754c0306425 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1673,7 +1673,7 @@ static void capture_reg_state(struct i915_gpu_state *error)
error->ccid = I915_READ(CCID);
/* 3: Feature specific registers */
- if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) {
+ if (GT_GEN_RANGE(dev_priv, 6, 7)) {
error->gam_ecochk = I915_READ(GAM_ECOCHK);
error->gac_eco = I915_READ(GAC_ECO_BITS);
}
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5cc1ffa621a7..b5154891e0d7 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -3449,7 +3449,7 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
dev_priv->perf.oa.ops.read = gen8_oa_read;
dev_priv->perf.oa.ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
- if (GT_GEN(dev_priv, 8) || GT_GEN(dev_priv, 9)) {
+ if (GT_GEN_RANGE(dev_priv, 8, 9)) {
dev_priv->perf.oa.ops.is_valid_b_counter_reg =
gen7_is_valid_b_counter_addr;
dev_priv->perf.oa.ops.is_valid_mux_reg =
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index dbc97c29f7e5..cbc76b7b8b74 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -322,7 +322,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (GT_GEN(dev_priv, 3) || GT_GEN(dev_priv, 4))
+ else if (GT_GEN_RANGE(dev_priv, 3, 4))
max_clock = 400000;
else
max_clock = 350000;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index bad3eb2428ac..1761529f3e69 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -783,7 +783,7 @@ void intel_device_info_runtime_init(struct intel_device_info *info)
DRM_INFO("Display disabled (module parameter)\n");
info->num_pipes = 0;
} else if (info->num_pipes > 0 &&
- (GT_GEN(dev_priv, 7) || GT_GEN(dev_priv, 8)) &&
+ (GT_GEN_RANGE(dev_priv, 7, 8)) &&
HAS_PCH_SPLIT(dev_priv)) {
u32 fuse_strap = I915_READ(FUSE_STRAP);
u32 sfuse_strap = I915_READ(SFUSE_STRAP);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 454a7e86adc8..0288169c1462 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -10684,7 +10684,7 @@ int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_stat
* the w/a on all three platforms.
*/
if (plane->id == PLANE_SPRITE0 &&
- (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6) ||
+ (GT_GEN_RANGE(dev_priv, 5, 6) ||
IS_IVYBRIDGE(dev_priv)) &&
(turn_on || (!needs_scaling(old_plane_state) &&
needs_scaling(to_intel_plane_state(plane_state)))))
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index fdd6966e5b95..db1a5d07e2e0 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -438,7 +438,7 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno)
* the semaphore value, then when the seqno moves backwards all
* future waits will complete instantly (causing rendering corruption).
*/
- if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7)) {
+ if (GT_GEN_RANGE(dev_priv, 6, 7)) {
I915_WRITE(RING_SYNC_0(engine->mmio_base), 0);
I915_WRITE(RING_SYNC_1(engine->mmio_base), 0);
if (HAS_VEBOX(dev_priv))
diff --git a/drivers/gpu/drm/i915/intel_fifo_underrun.c b/drivers/gpu/drm/i915/intel_fifo_underrun.c
index ff76da50153d..e1d48193ab0b 100644
--- a/drivers/gpu/drm/i915/intel_fifo_underrun.c
+++ b/drivers/gpu/drm/i915/intel_fifo_underrun.c
@@ -260,7 +260,7 @@ static bool __intel_set_cpu_fifo_underrun_reporting(struct drm_device *dev,
if (HAS_GMCH_DISPLAY(dev_priv))
i9xx_set_fifo_underrun_reporting(dev, pipe, enable, old);
- else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6))
+ else if (GT_GEN_RANGE(dev_priv, 5, 6))
ironlake_set_fifo_underrun_reporting(dev, pipe, enable);
else if (GT_GEN(dev_priv, 7))
ivybridge_set_fifo_underrun_reporting(dev, pipe, enable, old);
diff --git a/drivers/gpu/drm/i915/intel_pipe_crc.c b/drivers/gpu/drm/i915/intel_pipe_crc.c
index 597e52bc15e8..1ffa81f0be3c 100644
--- a/drivers/gpu/drm/i915/intel_pipe_crc.c
+++ b/drivers/gpu/drm/i915/intel_pipe_crc.c
@@ -433,7 +433,7 @@ static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv,
return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val);
- else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6))
+ else if (GT_GEN_RANGE(dev_priv, 5, 6))
return ilk_pipe_crc_ctl_reg(source, val);
else
return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val, set_wa);
@@ -550,7 +550,7 @@ intel_is_valid_crc_source(struct drm_i915_private *dev_priv,
return i9xx_crc_source_valid(dev_priv, source);
else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
return vlv_crc_source_valid(dev_priv, source);
- else if (GT_GEN(dev_priv, 5) || GT_GEN(dev_priv, 6))
+ else if (GT_GEN_RANGE(dev_priv, 5, 6))
return ilk_crc_source_valid(dev_priv, source);
else
return ivb_crc_source_valid(dev_priv, source);
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index f488cf5d1f43..88ffcde16fc6 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -528,7 +528,7 @@ check_for_unclaimed_mmio(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
ret |= vlv_check_for_unclaimed_mmio(dev_priv);
- if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))
+ if (GT_GEN_RANGE(dev_priv, 6, 7))
ret |= gen6_check_for_fifo_debug(dev_priv);
return ret;
@@ -556,7 +556,7 @@ static void __intel_uncore_early_sanitize(struct drm_i915_private *dev_priv,
dev_priv->uncore.funcs.force_wake_get(dev_priv,
restore_forcewake);
- if (GT_GEN(dev_priv, 6) || GT_GEN(dev_priv, 7))
+ if (GT_GEN_RANGE(dev_priv, 6, 7))
dev_priv->uncore.fifo_count =
fifo_free_entries(dev_priv);
spin_unlock_irq(&dev_priv->uncore.lock);
@@ -1437,7 +1437,7 @@ static void intel_uncore_fw_domains_init(struct drm_i915_private *dev_priv)
FORCEWAKE_MEDIA_VEBOX_GEN11(i),
FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(i));
}
- } else if (GT_GEN(dev_priv, 10) || GT_GEN(dev_priv, 9)) {
+ } else if (GT_GEN_RANGE(dev_priv, 9, 10)) {
dev_priv->uncore.funcs.force_wake_get =
fw_domains_get_with_fallback;
dev_priv->uncore.funcs.force_wake_put = fw_domains_put;
--
2.19.1.1.g56c4683e68
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