On Thu, Jul 05, 2012 at 01:27:47PM +0200, Daniel Vetter wrote:
> On Thu, May 24, 2012 at 09:08:55PM +0300, ville.syrjala at linux.intel.com wrote:
> > From: Ville Syrj?l? <ville.syrjala at linux.intel.com>
> >
> > Make sure the the framebuffer stride is smaller than the maximum
> > accepted by any plane.
> >
> > Also when using a tiled memory make sure the object stride matches
> > the framebuffer stride.
> >
> > Signed-off-by: Ville Syrj?l? <ville.syrjala at linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 18 ++++++++++++++++++
> > 1 files changed, 18 insertions(+), 0 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 7cf639c..8fea475 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -6643,6 +6643,17 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
> > .create_handle = intel_user_framebuffer_create_handle,
> > };
> >
> > +static unsigned int intel_max_fb_stride(const struct drm_device *dev)
> > +{
> > + /* FIXME: BSpec for pre-Gen5 is a bit unclear on stride limits */
> > + if (INTEL_INFO(dev)->gen <= 3)
> > + return 8192;
>
> 8k pitch limit is gen2, gen3 can have a 4kx4k framebuffer @32bit.
OK. I was just looking at BSpec but there were gaps in the docs. For
example, for gen3, only the limit for the OVL (8k) and tiled DSP (8k)
were mentioned. Nothing about non-tiled DSP. OTOH I don't know if even
the documented limits were really correct.
> -Daniel
>
> > + else if (INTEL_INFO(dev)->gen <= 4)
> > + return 16384;
>
> Iirc gen4 can also do 32k, see the pixel-based limits in
> intel_modset_init.
OK, BSpec was equally unclear here. Only tiled limit (16k) was
mentioned.
Seeing as the limits are a bit unclear, I don't know if I should even
try to add these checks. Unfortunately I don't have any pre-gen6
hardware, so I can't coax the real limits out of the hardware
empirically.
--
Ville Syrj?l?
Intel OTC
