Will do, I am not familiar with the procedure in Mesa but I will post a patch in their mailing list requesting for it to be included. I just had a chance to test this on a couple more mesa demo applications and 3DMarkmobile that also exhibit a lot of corruptions in Valleyview. The fix work well for those application as well. Douglas -----Original Message----- From: Jesse Barnes [mailto:jbarnes at virtuousgeek.org] Sent: Wednesday, July 04, 2012 3:28 AM To: Cheah, Douglas; intel-gfx at lists.freedesktop.org Subject: Re: Valleyview: 3DSTATE_URB_VS Minimum URB Entries "Cheah, Douglas" <douglas.cheah at intel.com> wrote: >Hello folks, > >I am seeing corruption when running spectex from mesa demos which looks >like vertex being randomly clipped on Valleyview, however spectex works >fine on Ivy Bridge. > >After tracing down the codes I realize that the current Mesa driver >would program the maximum number or URB entries (512 Valleyview) >whenever possible. This conflict with the 3D pipeline PRM where it >states there is a programming restriction if the URB Entry Allocation >Size is less than 9 URB entries then total entries should be program to >32. After modifying the codes to meet the restriction I was able to run >spectex without corruption on Valleyview, pretty surprise that Ivy >Bridge did not have this problem. > >Here is the code snippet that I have changed which is at this point a >quick hack and not upstream worthy as you can see the macro is not even >properly defined in brw_defeines.h. Appreciate if I could get opinions >from folks who are more familiar with Mesa and more experience with the >graphic core. > > >static void >gen7_upload_urb(struct brw_context *brw) { > struct intel_context *intel = &brw->intel; > /* Total space for entries is URB size - 16kB for push constants */ > int handle_region_size = (brw->urb.size - 16) * 1024; /* bytes */ > > /* CACHE_NEW_VS_PROG */ > brw->urb.vs_size = MAX2(brw->vs.prog_data->urb_entry_size, 1); > > int nr_vs_entries = handle_region_size / (brw->urb.vs_size * 64); > if (nr_vs_entries > brw->urb.max_vs_entries) > nr_vs_entries = brw->urb.max_vs_entries; > > /* If the number of URB Allocation Size is smaller than 9 512 bit > * units set the number or URB to Entries to 32 > */ >#define GEN7_URB_VS_MIN_ENTRIES 32 > if(brw->urb.vs_size < 9) > nr_vs_entries = GEN7_URB_VS_MIN_ENTRIES; > > > >Douglas >_______________________________________________ >Intel-gfx mailing list >Intel-gfx at lists.freedesktop.org >http://lists.freedesktop.org/mailman/listinfo/intel-gfx ooh this is a good fix. Can you bounce it over to the meas list for inclusion? -- Jesse Barnes, Intel Open Source Technology Center
