On Mon, 2 Jul 2012 11:51:08 -0300
Eugeni Dodonov <eugeni.dodonov at intel.com> wrote:
> We weren't disabling RC6 bits when bringing down RPS.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
Reviewed-by: Ben Widawsky <ben at bwidawsk.net>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b00df1f..5ea8319 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2303,6 +2303,7 @@ static void gen6_disable_rps(struct drm_device *dev)
> {
> struct drm_i915_private *dev_priv = dev->dev_private;
>
> + I915_WRITE(GEN6_RC_CONTROL, 0);
> I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
> I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
> I915_WRITE(GEN6_PMIER, 0);
I think we really only need to clear bit 31 to disable (and enable
already sets it to 0) but this should be fine.
--
Ben Widawsky, Intel Open Source Technology Center
