On Mon, 2 Jul 2012 11:51:03 -0300 Eugeni Dodonov <eugeni.dodonov at intel.com> wrote: > From: Chris Wilson <chris at chris-wilson.co.uk> > > As a w/a to prevent reads sporadically returning 0, we need to wait for > the GT thread to return to TC0 before proceeding to read the registers. > > v2: adapt for Haswell changes (Eugeni). > > v3: use wait_for_atomic_us for thread status polling. > > v3: *really* use wait_for_atomic for polling. > > References: https://bugs.freedesktop.org/show_bug.cgi?id=50243 > Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk> > Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com> meh, I cannot find the register defs, but since I've heard about this through the grapevine: Acked-by: Ben Widawsky <ben at bwidawsk.net> > --- > drivers/gpu/drm/i915/i915_drv.c | 22 ++++++++++++++++++++++ > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > 2 files changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c > index 928b667..a4ea4a9 100644 > --- a/drivers/gpu/drm/i915/i915_drv.c > +++ b/drivers/gpu/drm/i915/i915_drv.c > @@ -433,6 +433,22 @@ bool i915_semaphore_is_enabled(struct drm_device *dev) > return 1; > } > > +static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) > +{ > + u32 gt_thread_status_mask; > + > + if (IS_HASWELL(dev_priv->dev)) > + gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; > + else > + gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; > + > + /* w/a for a sporadic read returning 0 by waiting for the GT > + * thread to wake up. > + */ > + if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) > + DRM_ERROR("GT thread status wait timed out\n"); > +} > + > static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > { > if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0, 500)) > @@ -442,6 +458,8 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) > > if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1), 500)) > DRM_ERROR("Force wake wait timed out\n"); > + > + __gen6_gt_wait_for_thread_c0(dev_priv); > } > > static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) > @@ -453,6 +471,8 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) > > if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1), 500)) > DRM_ERROR("Force wake wait timed out\n"); > + > + __gen6_gt_wait_for_thread_c0(dev_priv); > } > > /* > @@ -538,6 +558,8 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv) > > if (wait_for_atomic_us((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & 1), 500)) > DRM_ERROR("Force wake wait timed out\n"); > + > + __gen6_gt_wait_for_thread_c0(dev_priv); > } > > static void vlv_force_wake_put(struct drm_i915_private *dev_priv) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index d8f516b..20f7f0d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1458,6 +1458,10 @@ > #define DDRMPLL1 0X12c20 > #define PEG_BAND_GAP_DATA 0x14d68 > > +#define GEN6_GT_THREAD_STATUS_REG 0x13805c > +#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 > +#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16)) > + > #define GEN6_GT_PERF_STATUS 0x145948 > #define GEN6_RP_STATE_LIMITS 0x145994 > #define GEN6_RP_STATE_CAP 0x145998 -- Ben Widawsky, Intel Open Source Technology Center
