With display disabled, driver don't need to enable any power well
or load the DMC firmware.
The only thing that *_display_core_init will do when display is
disabled is call intel_pch_reset_handshake(), so PCH handshake
will be unset and in counterpart *_display_core_uninit() will
only disable DC.
The power wells enabled by BIOS during boot will be disabled in
futher patch.
Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_runtime_pm.c | 56 ++++++++++++++++---------
1 file changed, 36 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 3b2588a377a9..8b1c4d0db0af 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3285,6 +3285,9 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
/* enable PCH reset handshake */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* enable PG1 and Misc I/O */
mutex_lock(&power_domains->lock);
@@ -3296,8 +3299,7 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
- if (INTEL_INFO(dev_priv)->num_pipes)
- skl_init_cdclk(dev_priv);
+ skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3312,10 +3314,12 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes)
- skl_uninit_cdclk(dev_priv);
+ skl_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
/* disable PG1 and Misc I/O */
@@ -3352,6 +3356,9 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
*/
intel_pch_reset_handshake(dev_priv, false);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* Enable PG1 */
mutex_lock(&power_domains->lock);
@@ -3360,8 +3367,7 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
- if (INTEL_INFO(dev_priv)->num_pipes)
- bxt_init_cdclk(dev_priv);
+ bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
@@ -3376,10 +3382,12 @@ void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
gen9_dbuf_disable(dev_priv);
- if (INTEL_INFO(dev_priv)->num_pipes)
- bxt_uninit_cdclk(dev_priv);
+ bxt_uninit_cdclk(dev_priv);
/* The spec doesn't call for removing the reset handshake flag */
@@ -3475,6 +3483,9 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 1. Enable PCH Reset Handshake */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
/* 2. Enable Comp */
val = I915_READ(CHICKEN_MISC_2);
val &= ~CNL_COMP_PWR_DOWN;
@@ -3502,8 +3513,7 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
mutex_unlock(&power_domains->lock);
/* 5. Enable CD clock */
- if (INTEL_INFO(dev_priv)->num_pipes)
- cnl_init_cdclk(dev_priv);
+ cnl_init_cdclk(dev_priv);
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
@@ -3520,14 +3530,16 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
gen9_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- if (INTEL_INFO(dev_priv)->num_pipes)
- cnl_uninit_cdclk(dev_priv);
+ cnl_uninit_cdclk(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
@@ -3560,6 +3572,9 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
/* 1. Enable PCH reset handshake. */
intel_pch_reset_handshake(dev_priv, !HAS_PCH_NOP(dev_priv));
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
for (port = PORT_A; port <= PORT_B; port++) {
/* 2. Enable DDI combo PHY comp. */
val = I915_READ(ICL_PHY_MISC(port));
@@ -3588,8 +3603,7 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
/* 5. Enable CDCLK. */
- if (INTEL_INFO(dev_priv)->num_pipes)
- icl_init_cdclk(dev_priv);
+ icl_init_cdclk(dev_priv);
/* 6. Enable DBUF. */
icl_dbuf_enable(dev_priv);
@@ -3610,14 +3624,16 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /* 1. Disable all display engine functions -> aready done */
+ if (!INTEL_INFO(dev_priv)->num_pipes)
+ return;
+
+ /* 1. Disable all display engine functions -> already done */
/* 2. Disable DBUF */
icl_dbuf_disable(dev_priv);
/* 3. Disable CD clock */
- if (INTEL_INFO(dev_priv)->num_pipes)
- icl_uninit_cdclk(dev_priv);
+ icl_uninit_cdclk(dev_priv);
/*
* 4. Disable Power Well 1 (PG1).
@@ -3784,11 +3800,11 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
skl_display_core_init(dev_priv, resume);
} else if (IS_GEN9_LP(dev_priv)) {
bxt_display_core_init(dev_priv, resume);
- } else if (IS_CHERRYVIEW(dev_priv)) {
+ } else if (IS_CHERRYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
mutex_unlock(&power_domains->lock);
- } else if (IS_VALLEYVIEW(dev_priv)) {
+ } else if (IS_VALLEYVIEW(dev_priv) && INTEL_INFO(dev_priv)->num_pipes) {
mutex_lock(&power_domains->lock);
vlv_cmnlane_wa(dev_priv);
mutex_unlock(&power_domains->lock);
--
2.19.1
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