On Fri, Feb 10, 2012 at 02:42:05PM -0200, Eugeni Dodonov wrote: > On Sat, Jan 28, 2012 at 20:48, Daniel Vetter <daniel.vetter at ffwll.ch> wrote: > > > The drm core _really_ likes to frob around with the crtc timings and > > put halfed vertical timings (in fields) in there. Which confuses the > > overlay code, resulting in it's refusal to display anything at the > > lower half of an interlaced pipe. > > > > Tested-by: Christopher Egert <cme3000 at gmail.com> > > Signed-Off-by: Daniel Vetter <daniel.vetter at ffwll.ch> > > > > This makes sense, and we have a test-case where it actually solves issues. > So > Reviewed-by: Eugeni Dodonov <eugeni.dodonov at intel.com> Ok, I've slurped this in for -next. Thanks a lot for patches, review, testing, crawling through docs and digging up register dumps from all over the place. -Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
