On Tue, 7 Feb 2012 10:28:30 +0100, Daniel Vetter <daniel at ffwll.ch> wrote:
> On Fri, Feb 03, 2012 at 02:31:40PM -0800, Ben Widawsky wrote:
> > - Add register definitions for GTFIFODBG.
> > - Capture it at error time.
> > - Print it from debugfs (with whitespace fix).
> >
> > This register tells us if either a read, or a write occured while the
> > fifo was full.
> >
> > Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
> > ---
> > drivers/gpu/drm/i915/i915_debugfs.c | 3 ++-
> > drivers/gpu/drm/i915/i915_drv.h | 1 +
> > drivers/gpu/drm/i915/i915_irq.c | 1 +
> > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++
> > drivers/gpu/drm/i915/intel_display.c | 3 +++
> > 5 files changed, 13 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> > index 6c3be86..f91a5d4 100644
> > --- a/drivers/gpu/drm/i915/i915_debugfs.c
> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> > @@ -760,7 +760,8 @@ static int i915_error_state(struct seq_file *m, void *unused)
> > seq_printf(m, "EIR: 0x%08x\n", error->eir);
> > seq_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
> > if (INTEL_INFO(dev)->gen >= 6) {
> > - seq_printf(m, "ERROR: 0x%08x\n", error->error);
> > + seq_printf(m, "ERROR: 0x%08x\n", error->error);
> > + seq_printf(m, "FIFODBG: 0x%08x\n", error->gtfifodbg);
> > seq_printf(m, "Blitter command stream:\n");
> > seq_printf(m, " ACTHD: 0x%08x\n", error->bcs_acthd);
> > seq_printf(m, " IPEIR: 0x%08x\n", error->bcs_ipeir);
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index f02a5f5..f02a57d 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -173,6 +173,7 @@ struct drm_i915_error_state {
> > u32 seqno;
> > u64 bbaddr;
> > u64 fence[I915_MAX_NUM_FENCES];
> > + u32 gtfifodbg;
> > struct timeval time;
> > struct drm_i915_error_object {
> > int page_count;
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index 5d433fc..d99592c 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -918,6 +918,7 @@ static void i915_capture_error_state(struct drm_device *dev)
> > error->error = 0;
> > if (INTEL_INFO(dev)->gen >= 6) {
> > error->error = I915_READ(ERROR_GEN6);
> > + error->gtfifodbg = I915_READ(GTFIFODBG);
> >
> > error->bcs_acthd = I915_READ(BCS_ACTHD);
> > error->bcs_ipehr = I915_READ(BCS_IPEHR);
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index c3afb78..1231c8e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3614,6 +3614,12 @@
> > #define ECOBUS 0xa180
> > #define FORCEWAKE_MT_ENABLE (1<<5)
> >
> > +#define GTFIFODBG 0x120000
> > +#define GT_FIFO_OVFERR (1<<2)
> > +#define GT_FIFO_CPU_ERROR_MASK 3
>
> Reading configdb it sounds like bit 2 is set when either bit 1 or bit 0 is
> set, but I might be wrong so imo it's better to check for all three bits.
>
> > +#define GT_FIFO_IAWRERR (1<<1)
> > +#define GT_FIFO_IARDERR (1<<0)
> > +
> > #define GT_FIFO_FREE_ENTRIES 0x120008
> > #define GT_FIFO_NUM_RESERVED_ENTRIES 20
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index ebe71ed..537f029 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8215,6 +8215,9 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
> > */
> > I915_WRITE(GEN6_RC_STATE, 0);
> > mutex_lock(&dev_priv->dev->struct_mutex);
> > + /* Clear the DBG now so we don't confuse earlier errors */
> > + I915_WRITE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
>
> I think we shouldn't silently clear errors here. Simplest might be a small
> inline helper to WARN_ON dirt in the gt fifo db reg - could be used in the
> later patches.
This reminds me, we have a few other error registers we should scrub upon init, along with the warning that something bad happened earlier.
-Chris
>
> > +
> > gen6_gt_force_wake_get(dev_priv);
> >
> > /* disable the counters and set deterministic thresholds */
> > --
> > 1.7.9
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx at lists.freedesktop.org
> > http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Mail: daniel at ffwll.ch
> Mobile: +41 (0)79 365 57 48
> _______________________________________________
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> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Chris Wilson, Intel Open Source Technology Centre
