On Fri, 3 Feb 2012 18:15:33 -0800, Ben Widawsky <ben at bwidawsk.net> wrote: > On Fri, Feb 03, 2012 at 11:10:09PM +0000, Chris Wilson wrote: > > On Fri, 3 Feb 2012 14:31:41 -0800, Ben Widawsky <ben at bwidawsk.net> wrote: > TBH, I don't really understand POSTING_READ that well. If it just > requires that any read request made it through to the MCH (or whatever), > then sure I can replace the POSTING_READ. Obviously though this is > reading GTFIFODBG, and not FORCEWAKE, so you tell me. The posting read is simply a PCI write/read ordering barrier. It can be a read of any mmio address and before it is performed all previous writes to mmio addresses must have been sent along the PCI and no subsequent write is allowed to emitted ahead of the read. Hmm, so since the writes are in fact weakly ordered (they are allowed to be emitted in any order so long as they not reordered past a read), we would strictly need a barrier in front of the write to disable forcewake if it were not for the buffering performed by the chip of mmio writes under rc6. -Chris -- Chris Wilson, Intel Open Source Technology Centre
