"Host modification in FBC does not trigger PSR to exit sleep state"
Since we are relying more on HW tracking lately it is better
to protect this gen10 displays.
Cc: Arthur J Runyan <arthur.j.runyan@xxxxxxxxx>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 8 ++++++++
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5530c470f30d..3ba720f133f0 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4027,6 +4027,7 @@ enum {
#define PWM1_GATING_DIS (1 << 13)
#define GEN9_CLKGATE_DIS_4 _MMIO(0x4653C)
+#define DPFC_GATING_DIS (1 << 31)
#define BXT_GMBUS_GATING_DIS (1 << 14)
#define _CLKGATE_DIS_PSL_A 0x46520
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7312ecb73415..56a46bc714c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -137,6 +137,9 @@ static void glk_init_clock_gating(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
+ /* WaPsrDisableDpfcClkGating:glk */
+ I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
+ DPFC_GATING_DIS);
}
static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
@@ -8715,6 +8718,11 @@ static void cnl_init_clock_gating(struct drm_i915_private *dev_priv)
val = I915_READ(UNSLICE_UNIT_LEVEL_CLKGATE);
val |= VFUNIT_CLKGATE_DIS;
I915_WRITE(UNSLICE_UNIT_LEVEL_CLKGATE, val);
+
+ /* WaPsrDisableDpfcClkGating:cnl (pre-prod) */
+ if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0))
+ I915_WRITE(GEN9_CLKGATE_DIS_4, I915_READ(GEN9_CLKGATE_DIS_4) |
+ DPFC_GATING_DIS);
}
static void cfl_init_clock_gating(struct drm_i915_private *dev_priv)
--
2.17.1
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