On Mon, Dec 10, 2012 at 12:44:11PM -0800, Jesse Barnes wrote:
> On Sat, 8 Dec 2012 12:58:33 +0100
> Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
>
> > We've originally added this in
> >
> > commit 291427f5fdadec6e4be2924172e83588880e1539
> > Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Date: Fri Jul 29 12:42:37 2011 -0700
> >
> > drm/i915: apply phase pointer override on SNB+ too
> >
> > and then copy-pasted it over to ivb/ppt. The w/a was originally added
> > for ilk/ibx in
> >
> > commit 5b2adf897146edeac6a1e438fb67b5a53dbbdf34
> > Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Date: Thu Oct 7 16:01:15 2010 -0700
> >
> > drm/i915: add Ironlake clock gating workaround for FDI link training
> >
> > and fixed up a bit in
> >
> > commit 6f06ce184c765fd8d50669a8d12fdd566c920859
> > Author: Jesse Barnes <jbarnes at virtuousgeek.org>
> > Date: Tue Jan 4 15:09:38 2011 -0800
> >
> > drm/i915: set phase sync pointer override enable before setting phase sync pointer
> >
> > It turns out that this w/a isn't actually required on cpt/ppt and
> > positively harmful on ivb/ppt when using fdi B/C links - it results in
> > a black screen occasionally, with seemingfully everything working as
> > it should. The only failure indication I've found in the hw is that
> > eventually (but not right after the modeset completes) a pipe underrun
> > is signalled.
> >
> > Big thanks to Arthur Runyan for all the ideas for registers to check
> > and changes to test, otherwise I couldn't ever have tracked this down!
> >
> > Cc: "Runyan, Arthur J" <arthur.j.runyan at intel.com>
> > Cc: stable at vger.kernel.org
> > Signed-off-by: Daniel Vetter <daniel.vetter at ffwll.ch>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 29 -----------------------------
> > 1 file changed, 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index b29259a..6929104 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -2335,18 +2335,6 @@ static void intel_fdi_normal_train(struct drm_crtc *crtc)
> > FDI_FE_ERRC_ENABLE);
> > }
> >
> > -static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
> > -{
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > - u32 flags = I915_READ(SOUTH_CHICKEN1);
> > -
> > - flags |= FDI_PHASE_SYNC_OVR(pipe);
> > - I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
> > - flags |= FDI_PHASE_SYNC_EN(pipe);
> > - I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
> > - POSTING_READ(SOUTH_CHICKEN1);
> > -}
> > -
> > static void ivb_modeset_global_resources(struct drm_device *dev)
> > {
> > struct drm_i915_private *dev_priv = dev->dev_private;
> > @@ -2521,8 +2509,6 @@ static void gen6_fdi_link_train(struct drm_crtc *crtc)
> > POSTING_READ(reg);
> > udelay(150);
> >
> > - cpt_phase_pointer_enable(dev, pipe);
> > -
> > for (i = 0; i < 4; i++) {
> > reg = FDI_TX_CTL(pipe);
> > temp = I915_READ(reg);
> > @@ -2655,8 +2641,6 @@ static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
> > POSTING_READ(reg);
> > udelay(150);
> >
> > - cpt_phase_pointer_enable(dev, pipe);
> > -
> > for (i = 0; i < 4; i++) {
> > reg = FDI_TX_CTL(pipe);
> > temp = I915_READ(reg);
> > @@ -2791,17 +2775,6 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
> > udelay(100);
> > }
> >
> > -static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
> > -{
> > - struct drm_i915_private *dev_priv = dev->dev_private;
> > - u32 flags = I915_READ(SOUTH_CHICKEN1);
> > -
> > - flags &= ~(FDI_PHASE_SYNC_EN(pipe));
> > - I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
> > - flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
> > - I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
> > - POSTING_READ(SOUTH_CHICKEN1);
> > -}
> > static void ironlake_fdi_disable(struct drm_crtc *crtc)
> > {
> > struct drm_device *dev = crtc->dev;
> > @@ -2828,8 +2801,6 @@ static void ironlake_fdi_disable(struct drm_crtc *crtc)
> > /* Ironlake workaround, disable clock pointer after downing FDI */
> > if (HAS_PCH_IBX(dev)) {
> > I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
> > - } else if (HAS_PCH_CPT(dev)) {
> > - cpt_phase_pointer_disable(dev, pipe);
> > }
> >
> > /* still set train pattern 1 */
>
> Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org>
Picked up for -fixes, thanks for the review.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
