I am not aware if there is a reason for restricting the Bytes per GMBUS WR/RD to 256 at present. But HW has 9Bits for Total Byte count for a single read or Write cycle. Means we can extend a cycle of RD/WR to 511Bytes. At present nothing much as ROI, as most of the usecases are for less than 256Bytes. On GLK tested for 300Bytes on single normal read, found to be working fine. First patch does it. But I have restricted the extension to Gen9 onwards, as I am not sure about the legacy platforms. And second patch is enabling the burst read for all GMBUS read of more than 511Bytes, on supported platforms. Basically this Burst read is enabled in HW for HDCP2.2 compliance requirement. Instead of enabling the burst read only for HDCP on special API this patch enables it for all GMBUS read of >511Bytes, on capable platforms. At present there is no clarity on special handling required for N*256 Bytes (Where N is >2). So as per discussions, at present we are fixing the max length for BURST read to 767 Bytes. Changes in V5 and V6: - Max length of Burst read is fixed at 767. [ville] - Collected Reviewed-by tags received. Ramalingam C (2): drm/i915/gmbus: Increase the Bytes per Rd/Wr Op drm/i915/gmbus: Enable burst read drivers/gpu/drm/i915/i915_drv.h | 3 ++ drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_i2c.c | 61 ++++++++++++++++++++++++++++++++-------- 3 files changed, 55 insertions(+), 11 deletions(-) -- 2.7.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
