== Series Details == Series: More ICL display patches (rev7) URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim checkpatch origin/drm-tip d9841751b963 drm/i915/icl: Extend AUX F interrupts to ICL 7913b8e944f7 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC 8b1806b8b1e1 drm/i915/icl: introduce tc_port dbbc1dcd8f1d drm/i915/icl: Support for TC North Display interrupts bb897d8be18f drm/i915/icp: Add Interrupt Support 23bec0ea27e5 drm/i915/ICL: Add register definition for DFLEXDPMLE 0aa9dd7d6752 drm/i915/icl: Add DDI HDMI level selection for ICL 0452d69471d2 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin ff4263dd5056 drm/i915/icl: Add Icelake PCH detection 914247ff4516 drm/i915/icl: add icelake_get_ddi_pll() 7aacef71bf5a drm/i915/icl: Get DDI clock for ICL based on PLLs. ea5e8efbb415 drm/i915/icl: Calculate link clock using the new registers 87436cc87084 drm/i915/icl: unconditionally init DDI for every port 089d3d15c278 drm/i915/icl: start adding the TBT pll -:162: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137: }; +#define I915_NUM_PLLS 7 total: 0 errors, 0 warnings, 1 checks, 129 lines checked 3292e78e766b drm/i915/icl: compute the TBT PLL registers -:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values> #18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455: +static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = { -:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values> #23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460: +static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = { total: 0 errors, 0 warnings, 2 checks, 51 lines checked 91188c6ba486 drm/i915/icl: Handle hotplug interrupts for DP over TBT c7b5b502d19d drm/i915/icl: Add 10-bit support for hdmi 8a7fe1b43d10 drm/i915/icl: implement icl_digital_port_connected() 6463e56dbfc4 drm/i915/icl: store the port type for TC ports 8e31a26476b9 drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP e86c6a8b3512 drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI 30221f17596f drm/i915/icl: Update FIA supported lane count for hpd. 76747abf5771 drm/i915/icl: program MG_DP_MODE 2a7fade59ca8 drm/i915/icl: toggle PHY clock gating around link training 0e9dc804376b drm/i915/icl: update VBT's child_device_config flags2 field _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
