From: Paulo Zanoni <paulo.r.zanoni at intel.com>
In order to retrain the link we have to disable everything, then
reenable.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 43 ++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_dp.c | 17 +++++++++-------
drivers/gpu/drm/i915/intel_drv.h | 1 +
3 files changed, 54 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 151963e..ed38bb3 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1125,3 +1125,46 @@ void intel_ddi_pll_init(struct drm_device *dev)
if (lcpll_needs_change)
I915_WRITE(LCPLL_CTL, lcpll_val);
}
+
+static void intel_ddi_enable_dp_port(struct intel_encoder *intel_encoder)
+{
+ struct drm_device *dev = intel_encoder->base.dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
+ int port = intel_dp->port;
+ uint32_t tp_val;
+
+ tp_val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST |
+ DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
+ if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
+ tp_val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
+ I915_WRITE(DP_TP_CTL(port), tp_val);
+ POSTING_READ(DP_TP_CTL(port));
+
+ intel_dp->DP |= DDI_BUF_CTL_ENABLE;
+ I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
+ POSTING_READ(DDI_BUF_CTL(port));
+
+ udelay(600);
+}
+
+void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
+{
+ struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
+ struct drm_crtc *crtc = encoder->crtc;
+ struct drm_crtc_helper_funcs *crtc_funcs;
+
+ if (!crtc) {
+ WARN(1, "Retraining encoder without crtc\n");
+ return;
+ }
+
+ crtc_funcs = crtc->helper_private;
+
+ intel_ddi_disable(encoder);
+
+ intel_ddi_pll_mode_set(crtc);
+ intel_ddi_enable_dp_port(intel_encoder);
+ intel_ddi_enable_pipe(intel_encoder);
+ (*crtc_funcs->dpms)(crtc, DRM_MODE_DPMS_ON);
+}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index e59d676..1feeac5 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1813,7 +1813,8 @@ intel_dp_set_link_train(struct intel_dp *intel_dp,
static void
intel_dp_start_link_train(struct intel_dp *intel_dp)
{
- struct drm_device *dev = intel_dp->base.base.dev;
+ struct drm_encoder *encoder = &intel_dp->base.base;
+ struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
int i;
@@ -1822,12 +1823,14 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
int voltage_tries, loop_tries;
uint32_t DP = intel_dp->DP;
- /*
- * On CPT we have to enable the port in training pattern 1, which
- * will happen below in intel_dp_set_link_train. Otherwise, enable
- * the port and wait for it to become active.
- */
- if (!HAS_PCH_CPT(dev)) {
+ if (IS_HASWELL(dev)) {
+ intel_ddi_prepare_link_retrain(encoder);
+ } else if (!HAS_PCH_CPT(dev)) {
+ /*
+ * On CPT we have to enable the port in training pattern 1,
+ * which will happen below in intel_dp_set_link_train.
+ * Otherwise, enable the port and wait for it to become active.
+ */
I915_WRITE(intel_dp->output_reg, intel_dp->DP);
POSTING_READ(intel_dp->output_reg);
intel_wait_for_vblank(dev, intel_crtc->pipe);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f3f5b83..a8ef8ca 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -535,5 +535,6 @@ extern void intel_ddi_mode_set(struct drm_encoder *encoder,
extern void intel_ddi_pll_init(struct drm_device *dev);
extern void intel_ddi_disable(struct drm_encoder *encoder);
extern void intel_ddi_commit(struct drm_encoder *encoder);
+extern void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder);
#endif /* __INTEL_DRV_H__ */
--
1.7.11.2
