[RFC 09/30] drm/i915: add DP support to intel_ddi_pll_mode_set

[przanoni at gmail.com (Paulo Zanoni)]

From: Paulo Zanoni <paulo.r.zanoni at intel.com>

Signed-off-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 39 ++++++++++++++++++++++++++++++++++-----
 1 file changed, 34 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 33b3a75..dd28e35 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -642,18 +642,23 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_encoder *intel_encoder;
 	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
-	bool is_hdmi = false, is_crt = false;
-	int port, i, to_use, num_encoders = 0;
+	bool is_hdmi = false, is_crt = false, is_dp = false;
+	int port = I915_MAX_PORTS, i, to_use, num_encoders = 0;
 	bool wrpll_used[] = {false, false};
 	bool spll_used = false;
 	uint32_t wrpll_reg[] = {WRPLL_CTL1, WRPLL_CTL2};
 	uint32_t wrpll_sel[] = {PORT_CLK_SEL_WRPLL1, PORT_CLK_SEL_WRPLL2};
 	uint32_t temp;
+	struct intel_dp *intel_dp = NULL;
+	struct intel_hdmi *intel_hdmi = NULL;
 
 	for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
-		struct intel_hdmi *intel_hdmi;
-
 		switch (intel_encoder->type) {
+		case INTEL_OUTPUT_DISPLAYPORT:
+			is_dp = true;
+			intel_dp = enc_to_intel_dp(&intel_encoder->base);
+			port = intel_dp->port;
+			break;
 		case INTEL_OUTPUT_HDMI:
 			is_hdmi = true;
 			intel_hdmi = enc_to_intel_hdmi(&intel_encoder->base);
@@ -678,6 +683,11 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
 		return false;
 	}
 
+	if (port == I915_MAX_PORTS) {
+		WARN(1, "No port selected\n");
+		return false;
+	}
+
 	for (i = PORT_A; i <= PORT_E; i++) {
 		if (i == port)
 			continue;
@@ -695,7 +705,26 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
 		}
 	}
 
-	if (is_hdmi) {
+	if (is_dp) {
+		switch (intel_dp->link_bw) {
+		case DP_LINK_BW_1_62:
+			temp = PORT_CLK_SEL_LCPLL_810;
+			break;
+		case DP_LINK_BW_2_7:
+			temp = PORT_CLK_SEL_LCPLL_1350;
+			break;
+		case DP_LINK_BW_5_4:
+			temp = PORT_CLK_SEL_LCPLL_2700;
+			break;
+		default:
+			DRM_ERROR("Link bandwidth %d unsupported\n",
+				  intel_dp->link_bw);
+			return false;
+		}
+
+		I915_WRITE(PORT_CLK_SEL(port), temp);
+
+	} else if (is_hdmi) {
 		int p, n2, r2;
 
 		for (i = 0; i < ARRAY_SIZE(wrpll_reg); i++)
-- 
1.7.11.2