== Series Details == Series: More ICL display patches URL : https://patchwork.freedesktop.org/series/43546/ State : warning == Summary == $ dim checkpatch origin/drm-tip 2ab358790967 drm/i915/icl: Extend AUX F interrupts to ICL 7f3648f2c0e1 drm/i915/icl: GSE interrupt moves from DE_MISC to GU_MISC 4b03c3e28a4a drm/i915/icl: introduce tc_port e145ad6bdaf7 drm/i915/icl: Support for TC North Display interrupts 4b11db5d4aee drm/i915/icp: Add Interrupt Support 25d4a67290ae drm/i915/ICL: Add register definition for DFLEXDPMLE e3cbd1343f5a drm/i915/icl: Add DDI HDMI level selection for ICL e2f7e7c949f8 drm/i915/icl: Map VBT DDC Pin to BSpec DDC Pin f70b5bcd4230 drm/i915/icl: Add Icelake PCH detection 20396ea4a008 drm/i915/icl: add icelake_get_ddi_pll() ea723cce4da2 drm/i915/icl: Get DDI clock for ICL based on PLLs. 8aeab8ca85b0 drm/i915/icl: Calculate link clock using the new registers ce32f58b49ab drm/i915/icl: unconditionally init DDI for every port 84be8b3f963c drm/i915/icl: start adding the TBT pll -:162: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #162: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.h:137: }; +#define I915_NUM_PLLS 7 total: 0 errors, 0 warnings, 1 checks, 129 lines checked eb581c948e8c drm/i915/icl: compute the TBT PLL registers -:18: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_24MHz_values> #18: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2455: +static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = { -:23: CHECK:CAMELCASE: Avoid CamelCase: <icl_tbt_pll_19_2MHz_values> #23: FILE: drivers/gpu/drm/i915/intel_dpll_mgr.c:2460: +static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = { total: 0 errors, 0 warnings, 2 checks, 51 lines checked bb11361a8af0 drm/i915/icl: Handle hotplug interrupts for DP over TBT 2eb44a94c4a2 drm/i915/icl: Add 10-bit support for hdmi 83cac5646aac drm/i915/icl: implement icl_digital_port_connected() dde729bf09c6 drm/i915/icl: store the port type for TC ports 38f287b089ee drm/i915/icl: implement the tc/legacy HPD {dis, }connect flow for DP cb0454d09ead drm/i915/icl: implement the legacy HPD {dis, }connect flow for HDMI 2732eb911ea5 drm/i915/icl: Update FIA supported lane count for hpd. 6f6990bdd31e drm/i915/icl: program MG_DP_MODE c9e0a92395b2 drm/i915/icl: toggle PHY clock gating around link training _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
