On Wed, Aug 22, 2012 at 12:03 PM, Lespiau, Damien <damien.lespiau at intel.com> wrote: > On Wed, Aug 22, 2012 at 11:46 AM, Lespiau, Damien > <damien.lespiau at intel.com> wrote: >> On Tue, Aug 21, 2012 at 7:11 PM, Daniel Vetter <daniel at ffwll.ch> wrote: >>>> Smoke-tested the new modeset-rework branch and found a regression on >>>> my IVB with a pristine f17 userland: >>>> >>>> * start with LVDS + VGA >>>> * unplug VGA >>>> * LVDS goes black >>> >>> Hm, not yet seen this one here. Can you attach a full dmesg with >>> drm.debug=0xe when this is happening, please? Adding more information to track this regression, a diff between the failure state and bringing back the panel with a off/on cycle (note the disabled DPLL). $ diff -u vga-out-lvds-fail.dump vga-out-lvds-off-on.dump --- vga-out-lvds-fail.dump 2012-08-22 14:05:44.732293487 +0100 +++ vga-out-lvds-off-on.dump 2012-08-22 14:06:21.690275915 +0100 @@ -28,10 +28,10 @@ PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000) PIPEA_LINK_M2: 0x00000000 (val 0x0 0) PIPEA_LINK_N2: 0x00000000 (val 0x0 0) - DSPACNTR: 0x58004400 (disabled) + DSPACNTR: 0xd8004400 (enabled) DSPABASE: 0x00000000 DSPASTRIDE: 0x00001600 (88) - DSPASURF: 0x041c6008 + DSPASURF: 0x0155c008 DSPATILEOFF: 0x00000000 (0, 0) PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc) HTOTAL_B: 0x0897077f (1920 active, 2200 total) @@ -102,7 +102,7 @@ PCH_SSC4_AUX_PARMS: 0x000029c5 PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null))) PCH_DPLL_ANALOG_CTL: 0x00008000 - PCH_DPLL_A: 0x08046004 (disable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1) + PCH_DPLL_A: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1) PCH_DPLL_B: 0x04020002 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 2, FPA1 P1 2, refclk default 120Mhz, sdvo/hdmi mul 1) PCH_FPA0: 0x00021108 (n = 2, m1 = 17, m2 = 8) PCH_FPA1: 0x00021108 (n = 2, m1 = 17, m2 = 8)