On 2012-08-22 06:15, Paulo Zanoni wrote:
> 2012/8/20 Ben Widawsky <ben at bwidawsk.net>:
>> ERR_INT on HSW will display unclaimed MMIO accesses. This can be
>> either
>> the result of a driver bug writing to an invalid addresses, or the
>> result of RC6.
>>
>> Signed-off-by: Ben Widawsky <ben at bwidawsk.net>
>
> For both patches:
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
> Tested-by: Paulo Zanoni <paulo.r.zanoni at intel.com>
>
> This is a pretty awesome change! It will really help the new hardware
> enablement/debugging efforts.
>
> We should volunteer someone to look at the other ERR_INT bits.
Consider yourself volunteered :-)
In all seriousness, I did look at the others. Nothing was as useful as
this one, IMO. There were a bunch of display related ones which I'm
fortunate enough to not have to fully understand. Having it in the error
state though over time might prove otherwise.
>
>> ---
>> drivers/gpu/drm/i915/i915_drv.c | 4 ++++
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> 2 files changed, 5 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.c
>> b/drivers/gpu/drm/i915/i915_drv.c
>> index 845e390..255087f 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.c
>> +++ b/drivers/gpu/drm/i915/i915_drv.c
>> @@ -1182,6 +1182,10 @@ void i915_write##x(struct drm_i915_private
>> *dev_priv, u32 reg, u##x val) { \
>> if (unlikely(__fifo_ret)) { \
>> gen6_gt_check_fifodbg(dev_priv); \
>> } \
>> + if (IS_HASWELL(dev_priv->dev) &&
>> (I915_READ_NOTRACE(GEN7_ERR_INT) & ERR_INT_MMIO_UNCLAIMED)) { \
>> + DRM_ERROR("Unclaimed write to %x\n", reg); \
>> + writel(ERR_INT_MMIO_UNCLAIMED, dev_priv->regs +
>> GEN7_ERR_INT); \
>> + } \
>> }
>> __i915_write(8, b)
>> __i915_write(16, w)
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h
>> b/drivers/gpu/drm/i915/i915_reg.h
>> index d4a7d73..bab4762 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -508,6 +508,7 @@
>>
>> #define ERROR_GEN6 0x040a0
>> #define GEN7_ERR_INT 0x44040
>> +#define ERR_INT_MMIO_UNCLAIMED (1<<13)
>>
>> /* GM45+ chicken bits -- debug workaround bits that may be required
>> * for various sorts of correct behavior. The top 16 bits of each
>> are
>> --
>> 1.7.11.5
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx at lists.freedesktop.org
>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ben Widawsky, Intel Open Source Technology Center
