On Fri, 2018-04-20 at 14:16 -0700, Rodrigo Vivi wrote:
> On Wed, Apr 18, 2018 at 03:43:08PM -0700, José Roberto de Souza
> wrote:
> > Sink can be configured to calculate the CRC over the static frame
> > and
> > compare with the CRC calculated and transmited in the VSC SDP by
> > source, if there is a mismatch sink will do a short pulse in HPD
> > and set DP_PSR_LINK_CRC_ERROR on DP_PSR_ERROR_STATUS.
>
> good idea, but first we need to stop using sink crc for the tests :(
We do the sink crc tests to check if PSR really exited and the screen
was updated with the new frame right? I don't see how this would cause
any problems.
>
> and make sure the interrupts are being handled correct...
>
> (I was going to mention an extra requirement that was to make sure
> that you implement the needed Wa, but I noticed you already took care
> of this)
>
> >
> > Also spec recommends to disable MAX_SLEEP as a trigger to exit PSR
> > when
> > CRC check is enabled to improve power savings.
>
> my first impression was that this should be a separated patch
> in case we needed to revert it doesn't revert both functionalities...
>
> however I saw this was Display WA #0388 with a mention:
> "This becomes standard required programming for all subsequent
> projects."
>
> so yeah, it belongs here. Maybe good to at least referrence this wa
> number.
I will add this.
>
> >
> > Spec: 7723
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@xxxxxxxxx>
> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@xxxxxxxxx>
> > Cc: Rodrigo Vivi <rodrigo.vivi@xxxxxxxxx>
> > ---
> >
> > Changes from v1:
> > - printing a debug message when sink assert a error
> >
> > drivers/gpu/drm/i915/i915_reg.h | 1 +
> > drivers/gpu/drm/i915/intel_psr.c | 24 +++++++++++++++++-------
> > 2 files changed, 18 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index fb106026a1f4..d3efbd654889 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -4016,6 +4016,7 @@ enum {
> > #define EDP_PSR_SKIP_AUX_EXIT (1<<12)
> > #define EDP_PSR_TP1_TP2_SEL (0<<11)
> > #define EDP_PSR_TP1_TP3_SEL (1<<11)
> > +#define EDP_PSR_CRC_ENABLE (1<<10) /*
> > BDW+ */
> > #define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
> > #define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
> > #define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 558b08a43f9e..1920e7d03e06 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -290,6 +290,8 @@ static void hsw_psr_enable_sink(struct intel_dp
> > *intel_dp)
> > dpcd_val |= DP_PSR_ENABLE_PSR2;
> > if (dev_priv->psr.link_standby)
> > dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE;
> > + if (!dev_priv->psr.psr2_enabled && INTEL_GEN(dev_priv) >=
> > 8)
> > + dpcd_val |= DP_PSR_CRC_VERIFICATION;
> > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
> > dpcd_val);
> >
> > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
> > DP_SET_POWER_D0);
> > @@ -377,6 +379,9 @@ static void hsw_activate_psr1(struct intel_dp
> > *intel_dp)
> > else
> > val |= EDP_PSR_TP1_TP2_SEL;
> >
> > + if (INTEL_GEN(dev_priv) >= 8)
> > + val |= EDP_PSR_CRC_ENABLE;
> > +
> > val |= I915_READ(EDP_PSR_CTL) &
> > EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK;
> > I915_WRITE(EDP_PSR_CTL, val);
> > }
> > @@ -602,10 +607,12 @@ static void hsw_psr_enable_source(struct
> > intel_dp *intel_dp,
> > * preventing other hw tracking issues now we can
> > rely
> > * on frontbuffer tracking.
> > */
> > - I915_WRITE(EDP_PSR_DEBUG,
> > - EDP_PSR_DEBUG_MASK_MEMUP |
> > - EDP_PSR_DEBUG_MASK_HPD |
> > - EDP_PSR_DEBUG_MASK_LPSP);
> > + u32 val = EDP_PSR_DEBUG_MASK_MEMUP |
> > EDP_PSR_DEBUG_MASK_HPD
> > + | EDP_PSR_DEBUG_MASK_LPSP;
> > +
> > + if (INTEL_GEN(dev_priv) >= 8)
> > + val |= EDP_PSR_DEBUG_MASK_MAX_SLEEP;
> > + I915_WRITE(EDP_PSR_DEBUG, val);
> > }
> > }
> >
> > @@ -1161,14 +1168,17 @@ void
> > intel_psr_hpd_short_pulse_handle(struct intel_dp *intel_dp)
> > goto dpcd_error;
> > }
> >
> > - if (val & DP_PSR_RFB_STORAGE_ERROR) {
> > - DRM_DEBUG_KMS("PSR RFB storage error, exiting
> > PSR\n");
> > + if (val & (DP_PSR_RFB_STORAGE_ERROR |
> > DP_PSR_LINK_CRC_ERROR)) {
> > + if (val & DP_PSR_RFB_STORAGE_ERROR)
> > + DRM_DEBUG_KMS("PSR RFB storage error,
> > exiting PSR\n");
> > + if (val & DP_PSR_LINK_CRC_ERROR)
> > + DRM_DEBUG_KMS("PSR Link CRC error, exiting
> > PSR\n");
> > intel_psr_exit(dev_priv);
> > }
> > /* clear status register */
> > drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_ERROR_STATUS,
> > val);
> >
> > - /* TODO: handle other PSR/PSR2 errors */
> > + /* TODO: handle PSR2 errors */
> > dpcd_error:
> > intel_psr_schedule_activate_work(dev_priv);
> > not_enabled:
> > --
> > 2.17.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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