Hi, All One question puzzle me is the update point of some register like DSPASURF (7019Ch), in Bspec it mentioned that it is at "Start of vertical blank or pipe disbaled". So it means that if pipe disabled, the writing of DSPASURF have effect on hardware status once this writing complete and we do not need to wait some extra 20ms Or some vblank interval. But I observed during display mode setting of i915, when pipe disabled, it still use intel_wait_for_vblank() (used in ironlake_crtc_mode_set() ) to delay 50ms. So this should be unnecessary right ? Thanks Anhua -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20120815/e400bc15/attachment.html>
