== Series Details == Series: Optimize use of DBuf slices URL : https://patchwork.freedesktop.org/series/41180/ State : warning == Summary == $ dim checkpatch origin/drm-tip e2b3a175155d drm/i915/icl: track dbuf slice-2 status 5cc032e8d384 drm/i915/icl: Enable 2nd DBuf slice only when needed -:71: CHECK:SPACING: No space is necessary after a cast #71: FILE: drivers/gpu/drm/i915/intel_drv.h:145: +#define GBps(x) ((uint64_t) 1000 * MBps((x))) -:114: CHECK:BRACES: braces {} should be used on all arms of this statement #114: FILE: drivers/gpu/drm/i915/intel_pm.c:3795: + if (total_data_bw >= GBps(12) || num_active > 1) [...] + else { [...] -:116: CHECK:BRACES: Unbalanced braces around else statement #116: FILE: drivers/gpu/drm/i915/intel_pm.c:3797: + else { -:212: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #212: FILE: drivers/gpu/drm/i915/intel_runtime_pm.c:2645: + DRM_ERROR("DBus power %s timeout!\n", + enable ? "enable" : "disable"); total: 0 errors, 0 warnings, 4 checks, 219 lines checked 587921dcf1da drm/i915/icl: update ddb entry start/end mask during hw ddb readout _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
