On 3/23/2018 12:21 PM, Kumar, Abhay wrote:
-----Original Message-----
From: Jani Nikula [mailto:jani.nikula@xxxxxxxxxxxxxxx]
Sent: Wednesday, February 14, 2018 10:00 AM
To: Kumar, Abhay <abhay.kumar@xxxxxxxxx>; Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
Subject: Re: [PATCH] drm/i915: set minimum CD clock to twice the BCLK.
On Wed, 25 Oct 2017, abhay.kumar@xxxxxxxxx wrote:
From: Abhay Kumar <abhay.kumar@xxxxxxxxx>
In glk when device boots with only 1366x768 panel, HDA codec doesn't comeup.
This result in no audio forever as cdclk is < 96Mhz.
This chagne will ensure CD clock to be twice of BCLK.
So this issue was never resolved was it?
Summing up, I think the ideas for solution were in order of preference:
1) Tie higher cdclk requirement to audio component get/put power
callbacks, and bump up cdclk when audio requests power
2) Bump up cdclk during i915 probe, after that require higher cdclk only
when has_audio is true
3) Require higher cdclk whenever there are display outputs that are
capable of hda
4) Always require higher cdclk (this patch)
BR,
Jani.
First of all sorry for addressing this patch late as i got tied up in
something else.
Yes this bug is still there and never resolved.
we can also honour VBT field which says enable or disable Dynamic cdclk
and control this from BIOS.
Let me figure out best way and comeup with patch.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102937
Signed-off-by: Abhay Kumar <abhay.kumar@xxxxxxxxx>
---
drivers/gpu/drm/i915/intel_cdclk.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index e8884c2ade98..185a70f0921c 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -1920,7 +1920,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
/* According to BSpec, "The CD clock frequency must be at least twice
* the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
*/
- if (crtc_state->has_audio && INTEL_GEN(dev_priv) >= 9)
+ if (INTEL_GEN(dev_priv) >= 9)
min_cdclk = max(2 * 96000, min_cdclk);
if (min_cdclk > dev_priv->max_cdclk_freq) {
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