On Thu, Aug 02, 2012 at 09:06:48AM -0700, Ben Widawsky wrote: > On 2012-08-02 05:07, Vijay Purushothaman wrote: > >In Valleyview the DPLL and lane control registers are accessible only > >through side band fabric called DPIO. Added two tools to read and > >write > >registers residing in this space. > > Could I convince you to use the centralized read/write mmio functions? > Otherwise, everything seems fine to me here. I wonder whether we need some kernel interface for this, after all if the kernel touches this, too, things will blow up. Otoh the kernel only uses the dpio sideband regs at modeset time, so I guess the risk is minimal. -Daniel -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
