On Thu, 26 Apr 2012 15:21:06 -0300
Eugeni Dodonov <eugeni.dodonov at intel.com> wrote:
> The line time can be programmed according to the number of horizontal
> pixels vs effective pixel rate ratio.
>
> v2: improve comment as per Chris Wilson suggestion
>
> v3: incorporate latest changes in specs.
>
> Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index ea1ac15..8308da0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -4555,6 +4555,19 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
> (adjusted_mode->crtc_vsync_start - 1) |
> ((adjusted_mode->crtc_vsync_end - 1) << 16));
>
> + if (IS_HASWELL(dev)) {
> + temp = I915_READ(PIPE_WM_LINETIME(pipe));
> + temp &= ~PIPE_WM_LINETIME_MASK;
> +
> + /* The WM are computed with base on how long it takes to fill a single
> + * row at the given clock rate, multiplied by 8.
> + * */
> + temp |= PIPE_WM_LINETIME_TIME(
> + ((adjusted_mode->crtc_hdisplay * 1000) / adjusted_mode->clock) * 8);
> +
> + I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
> + }
> +
> /* pipesrc controls the size that is scaled from, which should
> * always be the user's requested size.
> */
We need to set the IPS line time as well, and can we do it in the WM
functions instead?
--
Jesse Barnes, Intel Open Source Technology Center
