On Fri, Apr 27, 2012 at 12:55:12PM -0700, Kenneth Graunke wrote: > Clearing bit 5 of CACHE_MODE_0 is necessary to prevent GPU hangs in > OpenGL programs such as Google MapsGL, Google Earth, and gzdoom when > using separate stencil buffers. Without it, the GPU tries to use the > LRA eviction policy, which isn't supported. This was supposed to be off > by default, but seems to be on for many machines. > > This cannot be done in gen6_init_clock_gating with most of the other > workaround bits; the render ring needs to exist. Otherwise, the > register write gets dropped on the floor (one printk will show it > changed, but a second printk immediately following shows the value > reverts to the old one). > > v2: Don't write the Gen6 registers on Gen7+. > > Cc: stable at kernel.org > Cc: Rob Castle <futuredub at gmail.com> > Cc: Eric Appleman <erappleman at gmail.com> > Cc: aaron667 at gmx.net > Cc: Keith Packard <keithp at keithp.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47535 > Signed-off-by: Kenneth Graunke <kenneth at whitecape.org> Reviewed-by: Daniel Vetter <daniel.vetter at ffwll.ch> Dave, would be great if you can include this patch into drm-fixes right away. It fixes gpu hangs on various apps when using HiZ on reported by a lot of ppl. And it would help if this lands earlier in sorting out some conflicts with drm-intel-next. Thanks, Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index b4bb1ef..9d24d65 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -568,6 +568,7 @@ > #define CM0_MASK_SHIFT 16 > #define CM0_IZ_OPT_DISABLE (1<<6) > #define CM0_ZR_OPT_DISABLE (1<<5) > +#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5) > #define CM0_DEPTH_EVICT_DISABLE (1<<4) > #define CM0_COLOR_EVICT_DISABLE (1<<3) > #define CM0_DEPTH_WRITE_DISABLE (1<<1) > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c > index f75806e..af76723 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -398,6 +398,16 @@ static int init_render_ring(struct intel_ring_buffer *ring) > return ret; > } > > + if (IS_GEN6(dev)) { > + /* From the Sandybridge PRM, volume 1 part 3, page 24: > + * "If this bit is set, STCunit will have LRA as replacement > + * policy. [...] This bit must be reset. LRA replacement > + * policy is not supported." > + */ > + I915_WRITE(CACHE_MODE_0, > + CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT); > + } > + > if (INTEL_INFO(dev)->gen >= 6) { > I915_WRITE(INSTPM, > INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); > -- > 1.7.10 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
