On Thu, 26 Apr 2012 21:33:02 +0200, Daniel Vetter <daniel.vetter at ffwll.ch> wrote:
> /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
> if (IS_GEN3(dev)) {
> - u32 tmp = I915_READ(MI_ARB_STATE);
> - if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
> - /* arb state is a masked write, so set bit + bit in mask */
> - tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
> + if (!(I915_READ(MI_ARB_STATE) & MI_ARB_C3_LP_WRITE_ENABLE)) {
> + u32 tmp = _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE);
> I915_WRITE(MI_ARB_STATE, tmp);
Just write the masked bit, the state before is irrelevant.
I can't spot any other shifts that look to be being used as a mask, so
whatever the outcome of the above bikeshedding:
Reviewed-by: Chris Wilson <chris at chris-wilson.co.uk>
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
