Hello
Here are some more ICL patches, now with the Combo & MG PLLs, some DP/HDMI
initialization code and a few misc fixes.
Again, the R-B tags already present in some of the patches (including those form
me) were given a long time ago, so they need to be re-issued due to the
rebasing.
Thanks,
Paulo
Arkadiusz Hiler (1):
drm/i915/icl: Calculate link clock using the new registers
Dhinakaran Pandiyan (1):
drm/i915/icl: HPD pin for port F
James Ausmus (1):
drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTL
Manasi Navare (7):
drm/i915/icl: Add register definitions for Combo PHY vswing sequences.
drm/i915/icl: Add Combo PHY DDI Buffer translation tables for Icelake.
drm/i915/icl: Implement voltage swing programming sequence for Combo
PHY DDI
drm/i915/icl: Add register defs for voltage swing sequences for MG PHY
DDI
drm/i915/icl: Add Voltage swing table for MG PHY DDI Buffer
drm/i915/icl: Implement voltage swing programming sequence for MG PHY
DDI
drm/i915/icl: Fix the DP Max Voltage for ICL
Nabendu Maiti (1):
drm/i915/icl: Added 5k source scaling support for Gen11 platform
Paulo Zanoni (6):
drm/i915/icl: add definitions for the ICL PLL registers
drm/i915/icl: add basic support for the ICL clocks
drm/i915/icl: compute the combo PHY (DPLL) HDMI registers
drm/i915/icl: compute the combo PHY (DPLL) DP registers
drm/i915/icl: compute the MG PLL registers
drm/i915/gen11: all the DDI ports on gen 11 support 4 lanes
drivers/gpu/drm/i915/i915_debugfs.c | 22 ++
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/i915_reg.h | 313 ++++++++++++++++-
drivers/gpu/drm/i915/intel_ddi.c | 529 +++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_display.c | 33 +-
drivers/gpu/drm/i915/intel_dpll_mgr.c | 642 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/i915/intel_dpll_mgr.h | 41 +++
drivers/gpu/drm/i915/intel_drv.h | 10 +
drivers/gpu/drm/i915/intel_hotplug.c | 3 +
9 files changed, 1569 insertions(+), 25 deletions(-)
--
2.14.3
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