On Wed, Apr 18, 2012 at 10:25:05AM +0100, Chris Wilson wrote:
> On gen2 and gen4, MI_EXE_FLUSH is actually an AGP flush bit and is
> documented as being must-be-zero. So obey the documentation, and separate
> the gen2 flush into its own little routine and share with gen3.
MI_EXE_FLUSH on gen4 is actually to invalidate state/instruction caches.
> This means that we can rename the existing render_ring_flush() to
> reflect the generation from which it first applies and remove the code
> for handling earlier generations from it.
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
... and it doesn't compile too well here, too ;-)
-Daniel
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 53 ++++++++++++++++++++++---------
> 1 file changed, 38 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index 04330e3..9c6a937 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -53,9 +53,35 @@ static inline int ring_space(struct intel_ring_buffer *ring)
> }
>
> static int
> -render_ring_flush(struct intel_ring_buffer *ring,
> - u32 invalidate_domains,
> - u32 flush_domains)
> +gen2_render_ring_flush(struct intel_ring_buffer *ring,
> + u32 invalidate_domains,
> + u32 flush_domains)
> +{
> + u32 cmd;
> + int ret;
> +
> + cmd = MI_FLUSH;
> + if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
> + cmd |= MI_NO_WRITE_FLUSH;
> +
> + if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> + cmd |= MI_READ_FLUSH;
> +
> + ret = intel_ring_begin(ring, 2);
> + if (ret)
> + return ret;
> +
> + intel_ring_emit(ring, cmd);
> + intel_ring_emit(ring, MI_NOOP);
> + intel_ring_advance(ring);
> +
> + return 0;
> +}
> +
> +static int
> +gen4_render_ring_flush(struct intel_ring_buffer *ring,
> + u32 invalidate_domains,
> + u32 flush_domains)
> {
> struct drm_device *dev = ring->dev;
> u32 cmd;
> @@ -90,17 +116,8 @@ render_ring_flush(struct intel_ring_buffer *ring,
> */
>
> cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
> - if ((invalidate_domains|flush_domains) &
> - I915_GEM_DOMAIN_RENDER)
> + if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
> cmd &= ~MI_NO_WRITE_FLUSH;
> - if (INTEL_INFO(dev)->gen < 4) {
> - /*
> - * On the 965, the sampler cache always gets flushed
> - * and this bit is reserved.
> - */
> - if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
> - cmd |= MI_READ_FLUSH;
> - }
> if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
> cmd |= MI_EXE_FLUSH;
>
> @@ -1295,7 +1312,10 @@ int intel_init_render_ring_buffer(struct drm_device *dev)
> ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY;
> } else {
> ring->add_request = i9xx_add_request;
> - ring->flush = render_ring_flush;
> + if (INTEL_INFO(dev)->gen < 4)
> + ring->flush = gen2_render_ring_flush;
> + else
> + ring->flush = gen4_render_ring_flush;
> ring->get_seqno = ring_get_seqno;
> ring->irq_get = i9xx_ring_get_irq;
> ring->irq_put = i9xx_ring_put_irq;
> @@ -1340,7 +1360,10 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
> * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
> * the special gen5 functions. */
> ring->add_request = i9xx_add_request;
> - ring->flush = render_ring_flush;
> + if (INTEL_INFO(dev)->gen < 4)
> + ring->flush = gen2_render_ring_flush;
> + else
> + ring->flush = gen4_render_ring_flush;
> ring->get_seqno = ring_get_seqno;
> ring->irq_get = i9xx_ring_get_irq;
> ring->irq_put = i9xx_ring_put_irq;
> --
> 1.7.10
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx at lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
