From: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx> GEN9 onwards bypass path allocation of 4 blocks was needed, as per hardware design. ICL doesn't require bypass path allocation of 4 DDB blocks, handling the same in this patch. v2 (from Paulo): - No need for a comment that says what the code already says. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> Signed-off-by: Mahesh Kumar <mahesh1.kumar@xxxxxxxxx> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@xxxxxxxxx> --- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 0b92ea1dbd40..11aac65d1543 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3778,7 +3778,8 @@ skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, ddb_size = INTEL_INFO(dev_priv)->ddb_size; WARN_ON(ddb_size == 0); - ddb_size -= 4; /* 4 blocks for bypass path allocation */ + if (INTEL_GEN(dev_priv) < 11) + ddb_size -= 4; /* 4 blocks for bypass path allocation */ /* * If the state doesn't change the active CRTC's, then there's -- 2.14.3 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
