On Fri, Apr 13, 2012 at 05:08:39PM -0300, Eugeni Dodonov wrote: > Haswell has different DIP control registers and offsets. > > Signed-off-by: Eugeni Dodonov <eugeni.dodonov at intel.com> I've read a bit through Bspec wrt dip writing and it looks like hsw is rather differen from previous chips: - with have a data reg for every type of dip - the bits in the ctl reg moved around completely ... so I guess this patch and the follow-on one are pretty bogus. One thing I've noticed is that intel_infoframe_index and intel_infoframe_flags have way too generic names, they're only useful to frob the dip ctl reg on pre-hsw afaics. I think we should rename them to i9xx_infoframe_ctl_inde and _flags or something similar. -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 16 ++++++++++++++++ > 1 file changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 05d98f2..8cc53fb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -3488,6 +3488,22 @@ > #define VLV_TVIDEO_DIP_GCP(pipe) \ > _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B) > > +/* Haswell DIP controls */ > +#define HSW_VIDEO_DIP_CTL_A 0x60200 > +#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220 > +#define HSW_VIDEO_DIP_GCP_A 0x60210 > + > +#define HSW_VIDEO_DIP_CTL_B 0x61200 > +#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220 > +#define HSW_VIDEO_DIP_GCP_B 0x61210 > + > +#define HSW_TVIDEO_DIP_CTL(pipe) \ > + _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B) > +#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \ > + _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B) > +#define HSW_TVIDEO_DIP_GCP(pipe) \ > + _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B) > + > #define _TRANS_HTOTAL_B 0xe1000 > #define _TRANS_HBLANK_B 0xe1004 > #define _TRANS_HSYNC_B 0xe1008 > -- > 1.7.10 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Mail: daniel at ffwll.ch Mobile: +41 (0)79 365 57 48
