On Mon, Apr 16, 2012 at 03:18:33PM +0100, Chris Wilson wrote:
> As we may kick off a delayed workqueue task to switch of the VDD lines, we
> need to complete that task prior to turning off the panel (which itself
> depends upon VDD being off).
>
> Signed-off-by: Chris Wilson <chris at chris-wilson.co.uk>
> Cc: Keith Packard <keithp at keithp.com>
I've looked a bit at this and I think we just need a call to
ironlake_panel_vdd_off_sync instead of the WARN. The work will do the
right thing when the vdd is already off, so no problem there.
What problem we have though is that when we call cancel_work_sync we're
holding the config mutex, which the vdd work needs, too. Which is a nice
deadlock (which can currently only happen at module unload). I guess we
need a vdd_power mutex in the intel_dp struct just for this, so that we
can cancel the work without holding it, but protect all the vdd state
tracking from concurrent changes, still. The work would the only grab the
vdd_power mutex.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_dp.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index f07652b..7c2b5e1 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -1040,6 +1040,12 @@ static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
> }
> }
>
> +static void ironlake_panel_vdd_off_flush(struct intel_dp *intel_dp)
> +{
> + cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
> + ironlake_panel_vdd_off_sync(intel_dp);
> +}
> +
> static void ironlake_panel_vdd_work(struct work_struct *__work)
> {
> struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
> @@ -1128,6 +1134,7 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
> DRM_DEBUG_KMS("Turn eDP power off\n");
>
> WARN(intel_dp->want_panel_vdd, "Cannot turn power off while VDD is on\n");
> + ironlake_panel_vdd_off_flush(intel_dp);
>
> pp = ironlake_get_pp_control(dev_priv);
> pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
> --
> 1.7.10
>
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--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
