On Thu, 19 Jan 2012 00:29:23 +1100 Peter Ross <pross at xvid.org> wrote: > This patch set enables enables interlaced mode output on > generation 3 and above chipsets. > > History here: https://bugs.freedesktop.org/show_bug.cgi?id=11220 > > It has been tested on the following hardware: > * ASUS P5E-VM-HDMI (G35_G) and LG 32FS4D (VGA and SDVO connectors) > * Intel DQ45CB (Q45_G) and Sony GDM 5411 (VGA connector) > * Toshiba Portege R500 (I935_GM) and Sony GDM 5411 CRT (VGA connector) > > PATCH HISTORY > Version 1. Initial cut. > Version 2. Set timings for gen3 and ILK/SB chipsets. > Allow interlaced output on HDMI connector. > > Peter Ross (3): > drm/i915: specify vertical timings in frame units for interlaced > modes (gen3+) > drm/i915: allow interlaced mode output on the SDVO connector > drm/i915: allow interlaced mode output on the HDMI connector > > drivers/gpu/drm/i915/intel_display.c | 14 ++++++++++++++ > drivers/gpu/drm/i915/intel_hdmi.c | 2 +- > drivers/gpu/drm/i915/intel_sdvo.c | 2 +- > 3 files changed, 16 insertions(+), 2 deletions(-) Cool, this series looks good. Reviewed-by: Jesse Barnes <jbarnes at virtuousgeek.org> Yi, can you give these patches a try with interlaced modes on SDVO and HDMI attached displays and reply with your tested-by? Thanks, -- Jesse Barnes, Intel Open Source Technology Center -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 836 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20120118/69b3c0c5/attachment-0001.pgp>
