On Tue, Nov 15, 2011 at 07:47:58PM +0100, Takashi Iwai wrote:
> At Fri, 11 Nov 2011 14:12:58 -0800,
> Simon Que wrote:
> >
> > If the firmware did not initialize the backlight PWM registers, set up a
> > default PWM frequency of 200 Hz. This is determined using the following
> > formula:
> >
> > freq = refclk / (128 * pwm_max)
> >
> > The PWM register allows the max PWM value to be set. So we want to use
> > the formula, where freq = 200:
> >
> > pwm_max = refclk / (128 * freq)
> >
> > This patch will, in the case of missing PWM register initialization
> > values, look for the reference clock frequency. Based on that, it sets
> > an appropriate max PWM value for a frequency of 200 Hz.
> >
> > If no refclk frequency is found, the max PWM will be zero, which results
> > in no change to the PWM registers.
> >
> > Signed-off-by: Simon Que <sque at chromium.org>
> > ---
> > drivers/gpu/drm/i915/intel_panel.c | 38 ++++++++++++++++++++++++++++++-----
> > 1 files changed, 32 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
> > index f15388c..dda5de2 100644
> > --- a/drivers/gpu/drm/i915/intel_panel.c
> > +++ b/drivers/gpu/drm/i915/intel_panel.c
> > @@ -32,6 +32,12 @@
> >
> > #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
> >
> > +/* These are used to calculate a reasonable default when firmware has not
> > + * configured a maximum PWM frequency, with 200Hz as the current default target.
> > + */
> > +#define DEFAULT_BACKLIGHT_PWM_FREQ 200
> > +#define BACKLIGHT_REFCLK_DIVISOR 128
> > +
> > void
> > intel_fixed_panel_mode(struct drm_display_mode *fixed_mode,
> > struct drm_display_mode *adjusted_mode)
> > @@ -129,12 +135,32 @@ static int is_backlight_combination_mode(struct drm_device *dev)
> > return 0;
> > }
> >
> > +static void i915_set_default_max_backlight(struct drm_i915_private *dev_priv)
> > +{
> > + u32 refclk_freq_mhz = 0;
> > + u32 max_pwm;
> > +
> > + if (HAS_PCH_SPLIT(dev_priv->dev))
> > + refclk_freq_mhz = I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
> > + else if (dev_priv->lvds_use_ssc)
> > + refclk_freq_mhz = dev_priv->lvds_ssc_freq;
> > +
> > + max_pwm = refclk_freq_mhz * 1000000 /
> > + (BACKLIGHT_REFCLK_DIVISOR * DEFAULT_BACKLIGHT_PWM_FREQ);
> > +
> > + if (HAS_PCH_SPLIT(dev_priv->dev))
> > + dev_priv->saveBLC_PWM_CTL2 = max_pwm << 16;
> > + else if (IS_PINEVIEW(dev_priv->dev))
> > + dev_priv->saveBLC_PWM_CTL = max_pwm << 17;
> > + else
> > + dev_priv->saveBLC_PWM_CTL = max_pwm << 16;
>
> Is the pineview case really correct?
> The special handling for pineview in some places in intel_panel.c is
> just for omitting the bit 0, IIRC. It doesn't mean that the value is
> twice larger.
>
> BTW, this handling of bit 0 seems necessary not only for pineview but
> for the older chips (gen < 4) in general, too, as being discussed in
> another thread of LKML. 915GM hits the with problem of bit-0, for
> example.
Do we still need this patch? If so, can you please address Takashi's
comment, on a quick check he seems to have a point.
-Daniel
--
Daniel Vetter
Mail: daniel at ffwll.ch
Mobile: +41 (0)79 365 57 48
