We currently have two module parameters that control GuC: "enable_guc_loading" and "enable_guc_submission".
Whenever we need i915.enable_guc_submission=1, we also need enable_guc_loading=1.
We also need enable_guc_loading=1 when we want to verify the HuC,
which is every time we have a HuC (but all platforms with HuC have a GuC and viceversa).
v2: Clarifying the commit message (Anusha)
v3: Unify seq_puts messages, correcting inconsistencies (Michal)
v4: Rebased
Cc: Michal Wajdeczko <michal.wajdeczko@xxxxxxxxx>
Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx>
Cc: Oscar Mateo <oscar.mateo@xxxxxxxxx>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@xxxxxxxxx>
Signed-off-by: Sujaritha Sundaresan <sujaritha.sundaresan@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 22 +++++----
drivers/gpu/drm/i915/i915_drv.h | 11 +++--
drivers/gpu/drm/i915/i915_gem_context.c | 2 +-
drivers/gpu/drm/i915/i915_gem_gtt.c | 2 +-
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/i915_params.c | 5 --
drivers/gpu/drm/i915/i915_params.h | 1 -
drivers/gpu/drm/i915/intel_guc_loader.c | 6 ++-
drivers/gpu/drm/i915/intel_uc.c | 83 ++++++++++++++++++---------------
9 files changed, 73 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index ca6fa6d..063fbe3 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1616,7 +1616,7 @@ static int i915_fbc_status(struct seq_file *m, void *unused)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
if (!HAS_FBC(dev_priv)) {
- seq_puts(m, "FBC unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -1783,7 +1783,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
unsigned int max_gpu_freq, min_gpu_freq;
if (!HAS_LLC(dev_priv)) {
- seq_puts(m, "unsupported on this chipset\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2336,8 +2336,11 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data)
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_uc_fw *huc_fw = &dev_priv->huc.fw;
- if (!HAS_HUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_puts(m, "HuC firmware status:\n");
seq_printf(m, "\tpath: %s\n", huc_fw->path);
@@ -2369,8 +2372,11 @@ static int i915_guc_load_status_info(struct seq_file *m, void *data)
struct intel_uc_fw *guc_fw = &dev_priv->guc.fw;
u32 tmp, i;
- if (!HAS_GUC_UCODE(dev_priv))
+ if (!HAS_GUC(dev_priv)){
+ seq_puts(m, "not supported\n");
return 0;
+ }
+
seq_printf(m, "GuC firmware status:\n");
seq_printf(m, "\tpath: %s\n",
@@ -2465,7 +2471,7 @@ static bool check_guc_submission(struct seq_file *m)
if (!guc->execbuf_client) {
seq_printf(m, "GuC submission %s\n",
- HAS_GUC_SCHED(dev_priv) ?
+ HAS_GUC(dev_priv) ?
"disabled" :
"not supported");
return false;
@@ -2654,7 +2660,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
bool enabled = false;
if (!HAS_PSR(dev_priv)) {
- seq_puts(m, "PSR not supported\n");
+ seq_puts(m, "not supported\n");
return 0;
}
@@ -2807,7 +2813,7 @@ static int i915_runtime_pm_status(struct seq_file *m, void *unused)
struct pci_dev *pdev = dev_priv->drm.pdev;
if (!HAS_RUNTIME_PM(dev_priv))
- seq_puts(m, "Runtime power management not supported\n");
+ seq_puts(m, "not supported\n");
seq_printf(m, "GPU idle: %s\n", yesno(!dev_priv->gt.awake));
seq_printf(m, "IRQs disabled: %s\n",
@@ -3683,7 +3689,7 @@ static void drrs_status_per_crtc(struct seq_file *m,
mutex_unlock(&drrs->mutex);
} else {
/* DRRS not supported. Print the VBT parameter*/
- seq_puts(m, "\tDRRS Supported : No");
+ seq_puts(m, "not supported\n");
}
seq_puts(m, "\n");
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6d7d871..bd583f7 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3138,11 +3138,14 @@ static inline unsigned int i915_sg_segment_size(void)
* command submission once loaded. But these are logically independent
* properties, so we have separate macros to test them.
*/
-#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
-#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
-#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
-#define HAS_HUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
+#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
+#define HAS_GUC_UCODE(dev_priv) ((dev_priv)->guc.fw.path != NULL)
+#define HAS_HUC_UCODE(dev_priv) ((dev_priv)->huc.fw.path != NULL)
+
+#define NEEDS_GUC_LOADING(dev_priv) \
+ (HAS_GUC(dev_priv) && \
+ (i915.enable_guc_submission || HAS_HUC_UCODE(dev_priv)))
#define HAS_RESOURCE_STREAMER(dev_priv) ((dev_priv)->info.has_resource_streamer)
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 58a2a44..aaf3c03 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -314,7 +314,7 @@ static u32 default_desc_template(const struct drm_i915_private *i915,
* present or not in use we still need a small bias as ring wraparound
* at offset 0 sometimes hangs. No idea why.
*/
- if (HAS_GUC(dev_priv) && i915.enable_guc_loading)
+ if (NEEDS_GUC_LOADING(dev_priv))
ctx->ggtt_offset_bias = GUC_WOPCM_TOP;
else
ctx->ggtt_offset_bias = I915_GTT_PAGE_SIZE;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 731ce22..c1aeefb 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3292,7 +3292,7 @@ int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv)
* currently don't have any bits spare to pass in this upper
* restriction!
*/
- if (HAS_GUC(dev_priv) && i915.enable_guc_loading) {
+ if (NEEDS_GUC_LOADING(dev_priv)) {
ggtt->base.total = min_t(u64, ggtt->base.total, GUC_GGTT_TOP);
ggtt->mappable_end = min(ggtt->mappable_end, ggtt->base.total);
}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4d0e8f7..a151688 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -3962,7 +3962,7 @@ void intel_irq_init(struct drm_i915_private *dev_priv)
for (i = 0; i < MAX_L3_SLICES; ++i)
dev_priv->l3_parity.remap_info[i] = NULL;
- if (HAS_GUC_SCHED(dev_priv))
+ if (NEEDS_GUC_LOADING(dev_priv))
dev_priv->pm_guc_events = GEN9_GUC_TO_HOST_INT_EVENT;
/* Let's track the enabled rps events */
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index ddda513..bd0571d 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -63,7 +63,6 @@ struct i915_params i915 __read_mostly = {
.verbose_state_checks = 1,
.nuclear_pageflip = 0,
.edp_vswing = 0,
- .enable_guc_loading = 0,
.enable_guc_submission = 0,
.guc_log_level = -1,
.guc_firmware_path = NULL,
@@ -201,10 +200,6 @@ struct i915_params i915 __read_mostly = {
"(0=use value from vbt [default], 1=low power swing(200mV),"
"2=default swing(400mV))");
-i915_param_named_unsafe(enable_guc_loading, int, 0400,
- "Enable GuC firmware loading "
- "(-1=auto, 0=never [default], 1=if available, 2=required)");
-
i915_param_named_unsafe(enable_guc_submission, int, 0400,
"Enable GuC submission "
"(-1=auto, 0=never [default], 1=if available, 2=required)");
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index ac84470..e783d0b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -44,7 +44,6 @@
func(int, disable_power_well); \
func(int, enable_ips); \
func(int, invert_brightness); \
- func(int, enable_guc_loading); \
func(int, enable_guc_submission); \
func(int, guc_log_level); \
func(char *, guc_firmware_path); \
diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c
index 8b0ae7f..273a452 100644
--- a/drivers/gpu/drm/i915/intel_guc_loader.c
+++ b/drivers/gpu/drm/i915/intel_guc_loader.c
@@ -411,9 +411,11 @@ int intel_guc_select_fw(struct intel_guc *guc)
guc->fw.major_ver_wanted = GLK_FW_MAJOR;
guc->fw.minor_ver_wanted = GLK_FW_MINOR;
} else {
- DRM_ERROR("No GuC firmware known for platform with GuC!\n");
- return -ENOENT;
+ if (HAS_GUC(dev_priv))
+ DRM_ERROR("No GuC FW known for a platform with GuC!\n");
+ return;
}
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index 0178ba4..b898486 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -62,36 +62,40 @@ static int __intel_uc_reset_hw(struct drm_i915_private *dev_priv)
void intel_uc_sanitize_options(struct drm_i915_private *dev_priv)
{
- if (!HAS_GUC(dev_priv)) {
- if (i915.enable_guc_loading > 0 ||
- i915.enable_guc_submission > 0)
- DRM_INFO("Ignoring GuC options, no hardware\n");
-
- i915.enable_guc_loading = 0;
- i915.enable_guc_submission = 0;
- return;
+ /* Verify hardware support */
+ if (!HAS_GUC(dev_priv)){
+ if (i915.enable_guc_submission > 0)
+ DRM_INFO("Ignoring GuC submission enable, no HW\n");
+ i915.enable_guc_submission = 0;
+ return;
}
-
- /* A negative value means "use platform default" */
- if (i915.enable_guc_loading < 0)
- i915.enable_guc_loading = HAS_GUC_UCODE(dev_priv);
-
- /* Verify firmware version */
- if (i915.enable_guc_loading) {
- if (HAS_HUC_UCODE(dev_priv))
- intel_huc_select_fw(&dev_priv->huc);
-
- if (intel_guc_select_fw(&dev_priv->guc))
- i915.enable_guc_loading = 0;
+
+ /* Verify firmware support */
+ if (!HAS_GUC_UCODE(dev_priv)){
+ if (i915.enable_guc_submission == 1){
+ DRM_INFO("Ignoring GuC submission enable, no FW\n");
+ i915.enable_guc_submission = 0;
+ return;
+ }
+
+ if (i915.enable_guc_submission < 0){
+ i915.enable_guc_submission = 0;
+ return;
+ }
+
+ /*
+ * If "required"(> 1), let it continue and we will fail later
+ * due to lack of firmware
+ */
}
-
- /* Can't enable guc submission without guc loaded */
- if (!i915.enable_guc_loading)
- i915.enable_guc_submission = 0;
-
- /* A negative value means "use platform default" */
- if (i915.enable_guc_submission < 0)
- i915.enable_guc_submission = HAS_GUC_SCHED(dev_priv);
+
+ /*
+ * A negative value means "use platform default" (enabled if we have
+ * survived to get here)
+ */
+ if (i915.enable_guc_submission < 0)
+ i915.enable_guc_submission = 1;
+
}
static void gen8_guc_raise_irq(struct intel_guc *guc)
@@ -106,6 +110,8 @@ void intel_uc_init_early(struct drm_i915_private *dev_priv)
struct intel_guc *guc = &dev_priv->guc;
intel_guc_ct_init_early(&guc->ct);
+ intel_guc_select_fw(&dev_priv->guc);
+ intel_huc_select_fw(&dev_priv->huc);
mutex_init(&guc->send_mutex);
guc->send = intel_guc_send_nop;
@@ -252,6 +258,8 @@ static void fetch_uc_fw(struct drm_i915_private *dev_priv,
void intel_uc_init_fw(struct drm_i915_private *dev_priv)
{
+ if(!HAS_GUC(dev_priv))
+ return;
fetch_uc_fw(dev_priv, &dev_priv->huc.fw);
fetch_uc_fw(dev_priv, &dev_priv->guc.fw);
}
@@ -333,7 +341,7 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
struct intel_guc *guc = &dev_priv->guc;
int ret, attempts;
- if (!i915.enable_guc_loading)
+ if (!NEEDS_GUC_LOADING(dev_priv))
return 0;
guc_disable_communication(guc);
@@ -423,18 +431,17 @@ int intel_uc_init_hw(struct drm_i915_private *dev_priv)
i915_ggtt_disable_guc(dev_priv);
DRM_ERROR("GuC init failed\n");
- if (i915.enable_guc_loading > 1 || i915.enable_guc_submission > 1)
+ if (i915.enable_guc_submission > 1){
+ DRM_NOTE("GuC is required, so marking the GPU as wedged\n");
ret = -EIO;
- else
- ret = 0;
- if (i915.enable_guc_submission) {
- i915.enable_guc_submission = 0;
+ } else if (i915.enable_guc_submission == 1) {
DRM_NOTE("Falling back from GuC submission to execlist mode\n");
- }
- i915.enable_guc_loading = 0;
- DRM_NOTE("GuC firmware loading disabled\n");
+ i915.enable_guc_submission = 0;
+ ret = 0;
+ } else
+ ret = 0;
return ret;
}
@@ -443,7 +450,7 @@ void intel_uc_fini_hw(struct drm_i915_private *dev_priv)
{
guc_free_load_err_log(&dev_priv->guc);
- if (!i915.enable_guc_loading)
+ if (!NEEDS_GUC_LOADING(dev_priv))
return;
if (i915.enable_guc_submission)
--
1.9.1
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