Along with below patches sharing some background details/design.
- On BXT, Display cannot generate an interrupt when in D3.
- Without display in D3, S0ix can be achieved, Power impact will be zero if d3 is blocked. PMCSR for Graphics/Display is irrelevant, as the power management for them is taken care by the PUNIT using RC6/DC9 hints and *not* through PMCSR write trigger.
So solution is based on below principles:
- Display should not be put into D3 for HPD to work.
- With D0+DC9 we can achieve S0ix and at the same time helps to get the interrupt.
- Using pci_save_state() during suspend to take control from OSPM and blocking D3, while resuming, giving back to OSPM by pci_restore_state().
- _DSM method is used to program pmc hpd control register to enable hpd during suspend.
Please have a look and send your comments/suggestions.
v1: Initial version sent as RFC.
v2: Updated version after addressing review comments from Imre,David.
v3: Updated version after addressing review commnets from Imre, Ville,
Chris.
v4: New version updated after bios changes on APL platform.
Animesh Manna (5):
drm/i915/bxt: Corrected the guid for bxt.
drm/i915/bxt: VBT changes for hpd as wakeup feature
drm/i915/bxt: Added _DSM call to set HPD_CTL.
drm/i915/bxt: Block D3 during suspend.
drm/i915: Enable HPD interrupts with master ctl interrupt
drivers/gpu/drm/i915/i915_drv.c | 5 +++
drivers/gpu/drm/i915/i915_drv.h | 3 ++
drivers/gpu/drm/i915/i915_irq.c | 69 +++++++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 8 ++++
drivers/gpu/drm/i915/intel_acpi.c | 59 ++++++++++++++++++++++++----
drivers/gpu/drm/i915/intel_bios.c | 4 ++
drivers/gpu/drm/i915/intel_runtime_pm.c | 3 +-
drivers/gpu/drm/i915/intel_vbt_defs.h | 3 +-
8 files changed, 141 insertions(+), 13 deletions(-)
--
1.9.1
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