Just reading through vol1c.4 of the bspec this evening and found something odd. Bit 11 of MI_MODE is "Invalidate UHPTR enable". Bit 12 of MI_MODE is "MI_FLUSH Enable" And, yet, in i915_reg.h: #define MI_MODE 0x0209c # define VS_TIMER_DISPATCH (1 << 6) # define MI_FLUSH_ENABLE (1 << 11) Are we off-by-one on MI_FLUSH_ENABLE? Seems like this would cause serious problems... -- keith.packard at intel.com -------------- next part -------------- A non-text attachment was scrubbed... Name: not available Type: application/pgp-signature Size: 827 bytes Desc: not available URL: <http://lists.freedesktop.org/archives/intel-gfx/attachments/20111128/19132ff8/attachment-0001.pgp>
