Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@xxxxxxxxx>
---
drivers/gpu/drm/i915/Makefile | 4 +-
drivers/gpu/drm/i915/i915_oa_kblgt2.c | 2989 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_kblgt2.h | 38 +
drivers/gpu/drm/i915/i915_oa_kblgt3.c | 3038 +++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_oa_kblgt3.h | 38 +
drivers/gpu/drm/i915/i915_perf.c | 30 +-
6 files changed, 6135 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt2.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt2.h
create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt3.c
create mode 100644 drivers/gpu/drm/i915/i915_oa_kblgt3.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index aabc660f94cb..859e1751d7ab 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -134,7 +134,9 @@ i915-y += i915_perf.o \
i915_oa_sklgt2.o \
i915_oa_sklgt3.o \
i915_oa_sklgt4.o \
- i915_oa_bxt.o
+ i915_oa_bxt.o \
+ i915_oa_kblgt2.o \
+ i915_oa_kblgt3.o
ifeq ($(CONFIG_DRM_I915_GVT),y)
i915-y += intel_gvt.o
diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.c b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
new file mode 100644
index 000000000000..6e3cca270b37
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.c
@@ -0,0 +1,2989 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_kblgt2.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
+};
+
+int i915_oa_n_builtin_metric_sets_kblgt2 = 18;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x166c01e0 },
+ { _MMIO(0x9888), 0x12170280 },
+ { _MMIO(0x9888), 0x12370280 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x1a4e0080 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x0a1b4000 },
+ { _MMIO(0x9888), 0x1c1c0001 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x042f1000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c8400 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0d2000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f6600 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x162c2200 },
+ { _MMIO(0x9888), 0x062d8000 },
+ { _MMIO(0x9888), 0x082d8000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x08133000 },
+ { _MMIO(0x9888), 0x00170020 },
+ { _MMIO(0x9888), 0x08170021 },
+ { _MMIO(0x9888), 0x10170000 },
+ { _MMIO(0x9888), 0x0633c000 },
+ { _MMIO(0x9888), 0x0833c000 },
+ { _MMIO(0x9888), 0x06370800 },
+ { _MMIO(0x9888), 0x08370840 },
+ { _MMIO(0x9888), 0x10370000 },
+ { _MMIO(0x9888), 0x0d933031 },
+ { _MMIO(0x9888), 0x0f933e3f },
+ { _MMIO(0x9888), 0x01933d00 },
+ { _MMIO(0x9888), 0x0393073c },
+ { _MMIO(0x9888), 0x0593000e },
+ { _MMIO(0x9888), 0x1d930000 },
+ { _MMIO(0x9888), 0x19930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190001f },
+ { _MMIO(0x9888), 0x51904400 },
+ { _MMIO(0x9888), 0x41900020 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c21 },
+ { _MMIO(0x9888), 0x47900061 },
+ { _MMIO(0x9888), 0x57904440 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900004 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53904444 },
+};
+
+static int
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_render_basic;
+ lens[n] = ARRAY_SIZE(mux_config_render_basic);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x1a4e0820 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f0032 },
+ { _MMIO(0x9888), 0x0a4f1891 },
+ { _MMIO(0x9888), 0x0c4f0e00 },
+ { _MMIO(0x9888), 0x0e4f003c },
+ { _MMIO(0x9888), 0x004f0d80 },
+ { _MMIO(0x9888), 0x024f003b },
+ { _MMIO(0x9888), 0x006c0002 },
+ { _MMIO(0x9888), 0x086c0100 },
+ { _MMIO(0x9888), 0x0c6c000c },
+ { _MMIO(0x9888), 0x0e6c0b00 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x081b8000 },
+ { _MMIO(0x9888), 0x0c1b4000 },
+ { _MMIO(0x9888), 0x0e1b8000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1c8000 },
+ { _MMIO(0x9888), 0x1c1c0024 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5bc000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x1a5c6000 },
+ { _MMIO(0x9888), 0x1c5c001b },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2000 },
+ { _MMIO(0x9888), 0x0c4c0208 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cfb00 },
+ { _MMIO(0x9888), 0x182c00be },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900158 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900821 },
+ { _MMIO(0x9888), 0x47900802 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900802 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900422 },
+ { _MMIO(0x9888), 0x53904444 },
+};
+
+static int
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_basic;
+ lens[n] = ARRAY_SIZE(mux_config_compute_basic);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x1b931001 },
+ { _MMIO(0x9888), 0x1d930001 },
+ { _MMIO(0x9888), 0x19934000 },
+ { _MMIO(0x9888), 0x1b958000 },
+ { _MMIO(0x9888), 0x1d950094 },
+ { _MMIO(0x9888), 0x19958000 },
+ { _MMIO(0x9888), 0x09e58000 },
+ { _MMIO(0x9888), 0x0be58000 },
+ { _MMIO(0x9888), 0x03e5c000 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900440 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900c21 },
+ { _MMIO(0x9888), 0x57900400 },
+ { _MMIO(0x9888), 0x49900042 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900024 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900841 },
+ { _MMIO(0x9888), 0x53900400 },
+};
+
+static int
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_render_pipe_profile;
+ lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900064 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900150 },
+ { _MMIO(0x9888), 0x21900151 },
+ { _MMIO(0x9888), 0x23900152 },
+ { _MMIO(0x9888), 0x25900153 },
+ { _MMIO(0x9888), 0x27900154 },
+ { _MMIO(0x9888), 0x29900155 },
+ { _MMIO(0x9888), 0x2b900156 },
+ { _MMIO(0x9888), 0x2d900157 },
+ { _MMIO(0x9888), 0x2f90015f },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_memory_reads;
+ lens[n] = ARRAY_SIZE(mux_config_memory_reads);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900160 },
+ { _MMIO(0x9888), 0x21900161 },
+ { _MMIO(0x9888), 0x23900162 },
+ { _MMIO(0x9888), 0x25900163 },
+ { _MMIO(0x9888), 0x27900164 },
+ { _MMIO(0x9888), 0x29900165 },
+ { _MMIO(0x9888), 0x2b900166 },
+ { _MMIO(0x9888), 0x2d900167 },
+ { _MMIO(0x9888), 0x2f900150 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_memory_writes;
+ lens[n] = ARRAY_SIZE(mux_config_memory_writes);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x141c8160 },
+ { _MMIO(0x9888), 0x161c8015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4eaaa0 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0e6c0b01 },
+ { _MMIO(0x9888), 0x006c0200 },
+ { _MMIO(0x9888), 0x026c000c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x001c0041 },
+ { _MMIO(0x9888), 0x061c4200 },
+ { _MMIO(0x9888), 0x081c4443 },
+ { _MMIO(0x9888), 0x0a1c4645 },
+ { _MMIO(0x9888), 0x0c1c7647 },
+ { _MMIO(0x9888), 0x041c7357 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x101c0000 },
+ { _MMIO(0x9888), 0x1a1c0000 },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4caa2a },
+ { _MMIO(0x9888), 0x0c4c02aa },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5515 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x11907fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900802 },
+ { _MMIO(0x9888), 0x47900842 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900842 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900800 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_extended;
+ lens[n] = ARRAY_SIZE(mux_config_compute_extended);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c0760 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8020 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1ce000 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2a00 },
+ { _MMIO(0x9888), 0x0c4c0280 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f1500 },
+ { _MMIO(0x9888), 0x100f0140 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x182c00a0 },
+ { _MMIO(0x9888), 0x03933300 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190030f },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900021 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x53904444 },
+ { _MMIO(0x9888), 0x43900000 },
+};
+
+static int
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_l3_cache;
+ lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x106c0232 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x004f1880 },
+ { _MMIO(0x9888), 0x024f08bb },
+ { _MMIO(0x9888), 0x044f001b },
+ { _MMIO(0x9888), 0x046c0100 },
+ { _MMIO(0x9888), 0x066c000b },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x041b8000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025bc000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x165c8000 },
+ { _MMIO(0x9888), 0x185c8000 },
+ { _MMIO(0x9888), 0x0a4c00a0 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x062cc000 },
+ { _MMIO(0x9888), 0x082cc000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x1d950080 },
+ { _MMIO(0x9888), 0x13928000 },
+ { _MMIO(0x9888), 0x0f988000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900040 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_hdc_and_sf;
+ lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x126c7b40 },
+ { _MMIO(0x9888), 0x166c0020 },
+ { _MMIO(0x9888), 0x0a603444 },
+ { _MMIO(0x9888), 0x0a613400 },
+ { _MMIO(0x9888), 0x1a4ea800 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0800 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x1c1c003c },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x10600000 },
+ { _MMIO(0x9888), 0x04600000 },
+ { _MMIO(0x9888), 0x0c610044 },
+ { _MMIO(0x9888), 0x10610000 },
+ { _MMIO(0x9888), 0x06610000 },
+ { _MMIO(0x9888), 0x0c4c02a8 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0154 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190ffc0 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900021 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900400 },
+ { _MMIO(0x9888), 0x43900421 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static int
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_1;
+ lens[n] = ARRAY_SIZE(mux_config_l3_1);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x126c02e0 },
+ { _MMIO(0x9888), 0x146c0001 },
+ { _MMIO(0x9888), 0x0a623400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x026c3324 },
+ { _MMIO(0x9888), 0x046c3422 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x06614000 },
+ { _MMIO(0x9888), 0x0c620044 },
+ { _MMIO(0x9888), 0x10620000 },
+ { _MMIO(0x9888), 0x06620000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_2;
+ lens[n] = ARRAY_SIZE(mux_config_l3_2);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x126c4e80 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x0a633400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x026c3321 },
+ { _MMIO(0x9888), 0x046c342f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c2000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x06604000 },
+ { _MMIO(0x9888), 0x0c630044 },
+ { _MMIO(0x9888), 0x10630000 },
+ { _MMIO(0x9888), 0x06630000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c00aa },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_3;
+ lens[n] = ARRAY_SIZE(mux_config_l3_3);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102f3800 },
+ { _MMIO(0x9888), 0x144d0500 },
+ { _MMIO(0x9888), 0x120d03c0 },
+ { _MMIO(0x9888), 0x140d03cf },
+ { _MMIO(0x9888), 0x0c0f0004 },
+ { _MMIO(0x9888), 0x0c4e4000 },
+ { _MMIO(0x9888), 0x042f0480 },
+ { _MMIO(0x9888), 0x082f0000 },
+ { _MMIO(0x9888), 0x022f0000 },
+ { _MMIO(0x9888), 0x0a4c0090 },
+ { _MMIO(0x9888), 0x064d0027 },
+ { _MMIO(0x9888), 0x004d0000 },
+ { _MMIO(0x9888), 0x000d0d40 },
+ { _MMIO(0x9888), 0x020d803f },
+ { _MMIO(0x9888), 0x040d8023 },
+ { _MMIO(0x9888), 0x100d0000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020f0010 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x0e0f0050 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x43901485 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_rasterizer_and_pixel_backend;
+ lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x14152c00 },
+ { _MMIO(0x9888), 0x16150005 },
+ { _MMIO(0x9888), 0x121600a0 },
+ { _MMIO(0x9888), 0x14352c00 },
+ { _MMIO(0x9888), 0x16350005 },
+ { _MMIO(0x9888), 0x123600a0 },
+ { _MMIO(0x9888), 0x14552c00 },
+ { _MMIO(0x9888), 0x16550005 },
+ { _MMIO(0x9888), 0x125600a0 },
+ { _MMIO(0x9888), 0x062f6000 },
+ { _MMIO(0x9888), 0x022f2000 },
+ { _MMIO(0x9888), 0x0c4c0050 },
+ { _MMIO(0x9888), 0x0a4c0010 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0350 },
+ { _MMIO(0x9888), 0x0c0fb000 },
+ { _MMIO(0x9888), 0x0e0f00da },
+ { _MMIO(0x9888), 0x182c0028 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x022dc000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x0c138000 },
+ { _MMIO(0x9888), 0x0e132000 },
+ { _MMIO(0x9888), 0x0413c000 },
+ { _MMIO(0x9888), 0x1c140018 },
+ { _MMIO(0x9888), 0x0c157000 },
+ { _MMIO(0x9888), 0x0e150078 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04162180 },
+ { _MMIO(0x9888), 0x02160000 },
+ { _MMIO(0x9888), 0x04174000 },
+ { _MMIO(0x9888), 0x0233a000 },
+ { _MMIO(0x9888), 0x04333000 },
+ { _MMIO(0x9888), 0x14348000 },
+ { _MMIO(0x9888), 0x16348000 },
+ { _MMIO(0x9888), 0x02357870 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04360043 },
+ { _MMIO(0x9888), 0x02360000 },
+ { _MMIO(0x9888), 0x04371000 },
+ { _MMIO(0x9888), 0x0e538000 },
+ { _MMIO(0x9888), 0x00538000 },
+ { _MMIO(0x9888), 0x06533000 },
+ { _MMIO(0x9888), 0x1c540020 },
+ { _MMIO(0x9888), 0x12548000 },
+ { _MMIO(0x9888), 0x0e557000 },
+ { _MMIO(0x9888), 0x00557800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06560043 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x06571000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900060 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900060 },
+};
+
+static int
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_sampler;
+ lens[n] = ARRAY_SIZE(mux_config_sampler);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x12120000 },
+ { _MMIO(0x9888), 0x12320000 },
+ { _MMIO(0x9888), 0x12520000 },
+ { _MMIO(0x9888), 0x002f8000 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0015 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f03a0 },
+ { _MMIO(0x9888), 0x0c0ff000 },
+ { _MMIO(0x9888), 0x0e0f0095 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x02108000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x02118000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x02121880 },
+ { _MMIO(0x9888), 0x041219b5 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x02134000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x0c308000 },
+ { _MMIO(0x9888), 0x0e304000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x0c318000 },
+ { _MMIO(0x9888), 0x0e314000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x0c321a80 },
+ { _MMIO(0x9888), 0x0e320033 },
+ { _MMIO(0x9888), 0x06320031 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x0c334000 },
+ { _MMIO(0x9888), 0x0e331000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0e508000 },
+ { _MMIO(0x9888), 0x00508000 },
+ { _MMIO(0x9888), 0x02504000 },
+ { _MMIO(0x9888), 0x0e518000 },
+ { _MMIO(0x9888), 0x00518000 },
+ { _MMIO(0x9888), 0x02514000 },
+ { _MMIO(0x9888), 0x0e521880 },
+ { _MMIO(0x9888), 0x00521a80 },
+ { _MMIO(0x9888), 0x02520033 },
+ { _MMIO(0x9888), 0x0e534000 },
+ { _MMIO(0x9888), 0x00534000 },
+ { _MMIO(0x9888), 0x02531000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900062 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static int
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_tdl_1;
+ lens[n] = ARRAY_SIZE(mux_config_tdl_1);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x12124d60 },
+ { _MMIO(0x9888), 0x12322e60 },
+ { _MMIO(0x9888), 0x12524d60 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0014 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0fe000 },
+ { _MMIO(0x9888), 0x0e0f0097 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x002d8000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x04121fb7 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x00308000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x00318000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x00321b80 },
+ { _MMIO(0x9888), 0x0632003f },
+ { _MMIO(0x9888), 0x00334000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0250c000 },
+ { _MMIO(0x9888), 0x0251c000 },
+ { _MMIO(0x9888), 0x02521fb7 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x02535000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900063 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_tdl_2;
+ lens[n] = ARRAY_SIZE(mux_config_tdl_2);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+ { _MMIO(0xe458), 0x00001000 },
+ { _MMIO(0xe558), 0x00003002 },
+ { _MMIO(0xe658), 0x00005004 },
+ { _MMIO(0xe758), 0x00011010 },
+ { _MMIO(0xe45c), 0x00050012 },
+ { _MMIO(0xe55c), 0x00052051 },
+ { _MMIO(0xe65c), 0x00000008 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x121203e0 },
+ { _MMIO(0x9888), 0x123203e0 },
+ { _MMIO(0x9888), 0x125203e0 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0e0f006c },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x042d8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06114000 },
+ { _MMIO(0x9888), 0x06120033 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x04308000 },
+ { _MMIO(0x9888), 0x04318000 },
+ { _MMIO(0x9888), 0x04321980 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x04334000 },
+ { _MMIO(0x9888), 0x04504000 },
+ { _MMIO(0x9888), 0x04514000 },
+ { _MMIO(0x9888), 0x04520033 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x04531000 },
+ { _MMIO(0x9888), 0x1190e000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x43900c00 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_extra;
+ lens[n] = ARRAY_SIZE(mux_config_compute_extra);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x141a5800 },
+ { _MMIO(0x9888), 0x161a00c0 },
+ { _MMIO(0x9888), 0x12180240 },
+ { _MMIO(0x9888), 0x14180002 },
+ { _MMIO(0x9888), 0x143a5800 },
+ { _MMIO(0x9888), 0x163a00c0 },
+ { _MMIO(0x9888), 0x12380240 },
+ { _MMIO(0x9888), 0x14380002 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x022f8000 },
+ { _MMIO(0x9888), 0x042f3000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c1500 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f9500 },
+ { _MMIO(0x9888), 0x100f002a },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x0a2dc000 },
+ { _MMIO(0x9888), 0x0c2dc000 },
+ { _MMIO(0x9888), 0x04193000 },
+ { _MMIO(0x9888), 0x081a28c1 },
+ { _MMIO(0x9888), 0x001a0000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x0613c000 },
+ { _MMIO(0x9888), 0x0813f000 },
+ { _MMIO(0x9888), 0x00172000 },
+ { _MMIO(0x9888), 0x06178000 },
+ { _MMIO(0x9888), 0x0817a000 },
+ { _MMIO(0x9888), 0x00180037 },
+ { _MMIO(0x9888), 0x06180940 },
+ { _MMIO(0x9888), 0x08180000 },
+ { _MMIO(0x9888), 0x02180000 },
+ { _MMIO(0x9888), 0x04183000 },
+ { _MMIO(0x9888), 0x06393000 },
+ { _MMIO(0x9888), 0x0c3a28c1 },
+ { _MMIO(0x9888), 0x003a0000 },
+ { _MMIO(0x9888), 0x0a33f000 },
+ { _MMIO(0x9888), 0x0c33f000 },
+ { _MMIO(0x9888), 0x0a37a000 },
+ { _MMIO(0x9888), 0x0c37a000 },
+ { _MMIO(0x9888), 0x0a380977 },
+ { _MMIO(0x9888), 0x08380000 },
+ { _MMIO(0x9888), 0x04380000 },
+ { _MMIO(0x9888), 0x06383000 },
+ { _MMIO(0x9888), 0x119000ff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900800 },
+ { _MMIO(0x9888), 0x47901000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900844 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_vme_pipe;
+ lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x11810000 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_test_oa;
+ lens[n] = ARRAY_SIZE(mux_config_test_oa);
+ n++;
+
+ return n;
+}
+
+int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.n_mux_regs = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.n_mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
+ dev_priv->perf.oa.n_mux_regs =
+ get_memory_reads_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_reads;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_reads);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_reads;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.n_mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.n_mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.n_mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.n_mux_regs =
+ get_sampler_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.n_mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.n_mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.n_mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "f8d677e9-ff6f-4df1-9310-0334c6efacce",
+ .attrs = attrs_render_basic,
+};
+
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "e17fc42a-e614-41b6-90c4-1074841a6c77",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "d7a17a3a-ca71-40d2-a919-ace80d50633f",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "57b59202-172b-477a-87de-33f85572c589",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "4af0400a-81c3-47db-a6b6-deddbd75680e",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "0e22f995-79ca-4f67-83ab-e9d9772488d8",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "d2bbe790-f058-42d9-81c6-cdedcf655bc2",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "2f8e32e4-5956-46e2-af31-c8ea95887332",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "ca046aad-b5fb-4101-adce-6473ee6e5b14",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "605f388f-24bb-455c-88e3-8d57ae0d7e9f",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "105db928-5542-466b-9128-e1f3c91426cb",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "03db94d2-b37f-4c58-a791-0d2067b013bb",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "baa3c7e4-52b6-4b85-801e-465a94b746dd",
+ .attrs = attrs_test_oa,
+};
+
+int
+i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv)
+{
+ const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
+ int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
+
+ return 0;
+
+error_test_oa:
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv)
+{
+ const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
+ int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
+
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt2.h b/drivers/gpu/drm/i915/i915_oa_kblgt2.h
new file mode 100644
index 000000000000..1d64c76bb825
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt2.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_KBLGT2_H__
+#define __I915_OA_KBLGT2_H__
+
+extern int i915_oa_n_builtin_metric_sets_kblgt2;
+
+extern int i915_oa_select_metric_set_kblgt2(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_kblgt2(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_kblgt2(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.c b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
new file mode 100644
index 000000000000..0e81613dd0de
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.c
@@ -0,0 +1,3038 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <linux/sysfs.h>
+
+#include "i915_drv.h"
+#include "i915_oa_kblgt3.h"
+
+enum metric_set_id {
+ METRIC_SET_ID_RENDER_BASIC = 1,
+ METRIC_SET_ID_COMPUTE_BASIC,
+ METRIC_SET_ID_RENDER_PIPE_PROFILE,
+ METRIC_SET_ID_MEMORY_READS,
+ METRIC_SET_ID_MEMORY_WRITES,
+ METRIC_SET_ID_COMPUTE_EXTENDED,
+ METRIC_SET_ID_COMPUTE_L3_CACHE,
+ METRIC_SET_ID_HDC_AND_SF,
+ METRIC_SET_ID_L3_1,
+ METRIC_SET_ID_L3_2,
+ METRIC_SET_ID_L3_3,
+ METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND,
+ METRIC_SET_ID_SAMPLER,
+ METRIC_SET_ID_TDL_1,
+ METRIC_SET_ID_TDL_2,
+ METRIC_SET_ID_COMPUTE_EXTRA,
+ METRIC_SET_ID_VME_PIPE,
+ METRIC_SET_ID_TEST_OA,
+};
+
+int i915_oa_n_builtin_metric_sets_kblgt3 = 18;
+
+static const struct i915_oa_reg b_counter_config_render_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_render_basic[] = {
+ { _MMIO(0x9888), 0x166c01e0 },
+ { _MMIO(0x9888), 0x12170280 },
+ { _MMIO(0x9888), 0x12370280 },
+ { _MMIO(0x9888), 0x16ec01e0 },
+ { _MMIO(0x9888), 0x11930317 },
+ { _MMIO(0x9888), 0x159303df },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x1a4e0380 },
+ { _MMIO(0x9888), 0x0a6c0053 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x0a1b4000 },
+ { _MMIO(0x9888), 0x1c1c0001 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x042f1000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c8400 },
+ { _MMIO(0x9888), 0x0c4c0002 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f6600 },
+ { _MMIO(0x9888), 0x100f0001 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x162ca200 },
+ { _MMIO(0x9888), 0x062d8000 },
+ { _MMIO(0x9888), 0x082d8000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x08133000 },
+ { _MMIO(0x9888), 0x00170020 },
+ { _MMIO(0x9888), 0x08170021 },
+ { _MMIO(0x9888), 0x10170000 },
+ { _MMIO(0x9888), 0x0633c000 },
+ { _MMIO(0x9888), 0x0833c000 },
+ { _MMIO(0x9888), 0x06370800 },
+ { _MMIO(0x9888), 0x08370840 },
+ { _MMIO(0x9888), 0x10370000 },
+ { _MMIO(0x9888), 0x1ace0200 },
+ { _MMIO(0x9888), 0x0aec5300 },
+ { _MMIO(0x9888), 0x10ec0000 },
+ { _MMIO(0x9888), 0x1cec0000 },
+ { _MMIO(0x9888), 0x0a9b8000 },
+ { _MMIO(0x9888), 0x1c9c0002 },
+ { _MMIO(0x9888), 0x0ccc0002 },
+ { _MMIO(0x9888), 0x0a8d8000 },
+ { _MMIO(0x9888), 0x108f0001 },
+ { _MMIO(0x9888), 0x16ac8000 },
+ { _MMIO(0x9888), 0x0d933031 },
+ { _MMIO(0x9888), 0x0f933e3f },
+ { _MMIO(0x9888), 0x01933d00 },
+ { _MMIO(0x9888), 0x0393073c },
+ { _MMIO(0x9888), 0x0593000e },
+ { _MMIO(0x9888), 0x1d930000 },
+ { _MMIO(0x9888), 0x19930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x2b908000 },
+ { _MMIO(0x9888), 0x2d908000 },
+ { _MMIO(0x9888), 0x2f908000 },
+ { _MMIO(0x9888), 0x31908000 },
+ { _MMIO(0x9888), 0x15908000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190003f },
+ { _MMIO(0x9888), 0x51902240 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x55900242 },
+ { _MMIO(0x9888), 0x45900084 },
+ { _MMIO(0x9888), 0x47901400 },
+ { _MMIO(0x9888), 0x57902220 },
+ { _MMIO(0x9888), 0x49900c60 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900002 },
+ { _MMIO(0x9888), 0x43900c63 },
+ { _MMIO(0x9888), 0x53902222 },
+};
+
+static int
+get_render_basic_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_render_basic;
+ lens[n] = ARRAY_SIZE(mux_config_render_basic);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_basic[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2740), 0x00000000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_basic[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_basic[] = {
+ { _MMIO(0x9888), 0x104f00e0 },
+ { _MMIO(0x9888), 0x124f1c00 },
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x1a4e0820 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x064f0900 },
+ { _MMIO(0x9888), 0x084f0032 },
+ { _MMIO(0x9888), 0x0a4f1891 },
+ { _MMIO(0x9888), 0x0c4f0e00 },
+ { _MMIO(0x9888), 0x0e4f003c },
+ { _MMIO(0x9888), 0x004f0d80 },
+ { _MMIO(0x9888), 0x024f003b },
+ { _MMIO(0x9888), 0x006c0002 },
+ { _MMIO(0x9888), 0x086c0100 },
+ { _MMIO(0x9888), 0x0c6c000c },
+ { _MMIO(0x9888), 0x0e6c0b00 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x081b8000 },
+ { _MMIO(0x9888), 0x0c1b4000 },
+ { _MMIO(0x9888), 0x0e1b8000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1c8000 },
+ { _MMIO(0x9888), 0x1c1c0024 },
+ { _MMIO(0x9888), 0x065b8000 },
+ { _MMIO(0x9888), 0x085b4000 },
+ { _MMIO(0x9888), 0x0a5bc000 },
+ { _MMIO(0x9888), 0x0c5b8000 },
+ { _MMIO(0x9888), 0x0e5b4000 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025b4000 },
+ { _MMIO(0x9888), 0x1a5c6000 },
+ { _MMIO(0x9888), 0x1c5c001b },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2000 },
+ { _MMIO(0x9888), 0x0c4c0208 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020d2000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2cc000 },
+ { _MMIO(0x9888), 0x162cfb00 },
+ { _MMIO(0x9888), 0x182c00be },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x19900157 },
+ { _MMIO(0x9888), 0x1b900158 },
+ { _MMIO(0x9888), 0x1d900105 },
+ { _MMIO(0x9888), 0x1f900103 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x11900fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900821 },
+ { _MMIO(0x9888), 0x47900802 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900802 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900002 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900422 },
+ { _MMIO(0x9888), 0x53904444 },
+};
+
+static int
+get_compute_basic_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_basic;
+ lens[n] = ARRAY_SIZE(mux_config_compute_basic);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007ffea },
+ { _MMIO(0x2774), 0x00007ffc },
+ { _MMIO(0x2778), 0x0007affa },
+ { _MMIO(0x277c), 0x0000f5fd },
+ { _MMIO(0x2780), 0x00079ffa },
+ { _MMIO(0x2784), 0x0000f3fb },
+ { _MMIO(0x2788), 0x0007bf7a },
+ { _MMIO(0x278c), 0x0000f7e7 },
+ { _MMIO(0x2790), 0x0007fefa },
+ { _MMIO(0x2794), 0x0000f7cf },
+ { _MMIO(0x2798), 0x00077ffa },
+ { _MMIO(0x279c), 0x0000efdf },
+ { _MMIO(0x27a0), 0x0006fffa },
+ { _MMIO(0x27a4), 0x0000cfbf },
+ { _MMIO(0x27a8), 0x0003fffa },
+ { _MMIO(0x27ac), 0x00005f7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_render_pipe_profile[] = {
+ { _MMIO(0x9888), 0x0c0e001f },
+ { _MMIO(0x9888), 0x0a0f0000 },
+ { _MMIO(0x9888), 0x10116800 },
+ { _MMIO(0x9888), 0x178a03e0 },
+ { _MMIO(0x9888), 0x11824c00 },
+ { _MMIO(0x9888), 0x11830020 },
+ { _MMIO(0x9888), 0x13840020 },
+ { _MMIO(0x9888), 0x11850019 },
+ { _MMIO(0x9888), 0x11860007 },
+ { _MMIO(0x9888), 0x01870c40 },
+ { _MMIO(0x9888), 0x17880000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x0a4c0040 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x040d4000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020e5400 },
+ { _MMIO(0x9888), 0x000e0000 },
+ { _MMIO(0x9888), 0x080f0040 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x100f0000 },
+ { _MMIO(0x9888), 0x0e0f0040 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06110012 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x01898000 },
+ { _MMIO(0x9888), 0x0d890100 },
+ { _MMIO(0x9888), 0x03898000 },
+ { _MMIO(0x9888), 0x09808000 },
+ { _MMIO(0x9888), 0x0b808000 },
+ { _MMIO(0x9888), 0x0380c000 },
+ { _MMIO(0x9888), 0x0f8a0075 },
+ { _MMIO(0x9888), 0x1d8a0000 },
+ { _MMIO(0x9888), 0x118a8000 },
+ { _MMIO(0x9888), 0x1b8a4000 },
+ { _MMIO(0x9888), 0x138a8000 },
+ { _MMIO(0x9888), 0x1d81a000 },
+ { _MMIO(0x9888), 0x15818000 },
+ { _MMIO(0x9888), 0x17818000 },
+ { _MMIO(0x9888), 0x0b820030 },
+ { _MMIO(0x9888), 0x07828000 },
+ { _MMIO(0x9888), 0x0d824000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x05824000 },
+ { _MMIO(0x9888), 0x0d830003 },
+ { _MMIO(0x9888), 0x0583000c },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x03838000 },
+ { _MMIO(0x9888), 0x07838000 },
+ { _MMIO(0x9888), 0x0b840980 },
+ { _MMIO(0x9888), 0x03844d80 },
+ { _MMIO(0x9888), 0x11840000 },
+ { _MMIO(0x9888), 0x09848000 },
+ { _MMIO(0x9888), 0x09850080 },
+ { _MMIO(0x9888), 0x03850003 },
+ { _MMIO(0x9888), 0x01850000 },
+ { _MMIO(0x9888), 0x07860000 },
+ { _MMIO(0x9888), 0x0f860400 },
+ { _MMIO(0x9888), 0x09870032 },
+ { _MMIO(0x9888), 0x01888052 },
+ { _MMIO(0x9888), 0x11880000 },
+ { _MMIO(0x9888), 0x09884000 },
+ { _MMIO(0x9888), 0x1b931001 },
+ { _MMIO(0x9888), 0x1d930001 },
+ { _MMIO(0x9888), 0x19934000 },
+ { _MMIO(0x9888), 0x1b958000 },
+ { _MMIO(0x9888), 0x1d950094 },
+ { _MMIO(0x9888), 0x19958000 },
+ { _MMIO(0x9888), 0x09e58000 },
+ { _MMIO(0x9888), 0x0be58000 },
+ { _MMIO(0x9888), 0x03e5c000 },
+ { _MMIO(0x9888), 0x0592c000 },
+ { _MMIO(0x9888), 0x0b928000 },
+ { _MMIO(0x9888), 0x0d924000 },
+ { _MMIO(0x9888), 0x0f924000 },
+ { _MMIO(0x9888), 0x11928000 },
+ { _MMIO(0x9888), 0x1392c000 },
+ { _MMIO(0x9888), 0x09924000 },
+ { _MMIO(0x9888), 0x01985000 },
+ { _MMIO(0x9888), 0x07988000 },
+ { _MMIO(0x9888), 0x09981000 },
+ { _MMIO(0x9888), 0x0b982000 },
+ { _MMIO(0x9888), 0x0d982000 },
+ { _MMIO(0x9888), 0x0f989000 },
+ { _MMIO(0x9888), 0x05982000 },
+ { _MMIO(0x9888), 0x13904000 },
+ { _MMIO(0x9888), 0x21904000 },
+ { _MMIO(0x9888), 0x23904000 },
+ { _MMIO(0x9888), 0x25908000 },
+ { _MMIO(0x9888), 0x27904000 },
+ { _MMIO(0x9888), 0x29908000 },
+ { _MMIO(0x9888), 0x2b904000 },
+ { _MMIO(0x9888), 0x2f904000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x15904000 },
+ { _MMIO(0x9888), 0x17908000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b904000 },
+ { _MMIO(0x9888), 0x1190c080 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900440 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x47900c21 },
+ { _MMIO(0x9888), 0x57900400 },
+ { _MMIO(0x9888), 0x49900042 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900024 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900841 },
+ { _MMIO(0x9888), 0x53900400 },
+};
+
+static int
+get_render_pipe_profile_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_render_pipe_profile;
+ lens[n] = ARRAY_SIZE(mux_config_render_pipe_profile);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_reads[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f872 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_reads[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_reads[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f900064 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900150 },
+ { _MMIO(0x9888), 0x21900151 },
+ { _MMIO(0x9888), 0x23900152 },
+ { _MMIO(0x9888), 0x25900153 },
+ { _MMIO(0x9888), 0x27900154 },
+ { _MMIO(0x9888), 0x29900155 },
+ { _MMIO(0x9888), 0x2b900156 },
+ { _MMIO(0x9888), 0x2d900157 },
+ { _MMIO(0x9888), 0x2f90015f },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_memory_reads_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_memory_reads;
+ lens[n] = ARRAY_SIZE(mux_config_memory_reads);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_memory_writes[] = {
+ { _MMIO(0x272c), 0xffffffff },
+ { _MMIO(0x2728), 0xffffffff },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x271c), 0xffffffff },
+ { _MMIO(0x2718), 0xffffffff },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x274c), 0x86543210 },
+ { _MMIO(0x2748), 0x86543210 },
+ { _MMIO(0x2744), 0x00006667 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x275c), 0x86543210 },
+ { _MMIO(0x2758), 0x86543210 },
+ { _MMIO(0x2754), 0x00006465 },
+ { _MMIO(0x2750), 0x00000000 },
+ { _MMIO(0x2770), 0x0007f81a },
+ { _MMIO(0x2774), 0x0000fe00 },
+ { _MMIO(0x2778), 0x0007f82a },
+ { _MMIO(0x277c), 0x0000fe00 },
+ { _MMIO(0x2780), 0x0007f822 },
+ { _MMIO(0x2784), 0x0000fe00 },
+ { _MMIO(0x2788), 0x0007f8ba },
+ { _MMIO(0x278c), 0x0000fe00 },
+ { _MMIO(0x2790), 0x0007f87a },
+ { _MMIO(0x2794), 0x0000fe00 },
+ { _MMIO(0x2798), 0x0007f8ea },
+ { _MMIO(0x279c), 0x0000fe00 },
+ { _MMIO(0x27a0), 0x0007f8e2 },
+ { _MMIO(0x27a4), 0x0000fe00 },
+ { _MMIO(0x27a8), 0x0007f8f2 },
+ { _MMIO(0x27ac), 0x0000fe00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_memory_writes[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00015014 },
+ { _MMIO(0xe658), 0x00025024 },
+ { _MMIO(0xe758), 0x00035034 },
+ { _MMIO(0xe45c), 0x00045044 },
+ { _MMIO(0xe55c), 0x00055054 },
+ { _MMIO(0xe65c), 0x00065064 },
+};
+
+static const struct i915_oa_reg mux_config_memory_writes[] = {
+ { _MMIO(0x9888), 0x11810c00 },
+ { _MMIO(0x9888), 0x1381001a },
+ { _MMIO(0x9888), 0x37906800 },
+ { _MMIO(0x9888), 0x3f901000 },
+ { _MMIO(0x9888), 0x03811300 },
+ { _MMIO(0x9888), 0x05811b12 },
+ { _MMIO(0x9888), 0x0781001a },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x17810000 },
+ { _MMIO(0x9888), 0x19810000 },
+ { _MMIO(0x9888), 0x1b810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930055 },
+ { _MMIO(0x9888), 0x03e58000 },
+ { _MMIO(0x9888), 0x05e5c000 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x13900160 },
+ { _MMIO(0x9888), 0x21900161 },
+ { _MMIO(0x9888), 0x23900162 },
+ { _MMIO(0x9888), 0x25900163 },
+ { _MMIO(0x9888), 0x27900164 },
+ { _MMIO(0x9888), 0x29900165 },
+ { _MMIO(0x9888), 0x2b900166 },
+ { _MMIO(0x9888), 0x2d900167 },
+ { _MMIO(0x9888), 0x2f900150 },
+ { _MMIO(0x9888), 0x31900105 },
+ { _MMIO(0x9888), 0x15900103 },
+ { _MMIO(0x9888), 0x17900101 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1d908000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c60 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900c00 },
+ { _MMIO(0x9888), 0x47900c63 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900c63 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900063 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_memory_writes_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_memory_writes;
+ lens[n] = ARRAY_SIZE(mux_config_memory_writes);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extended[] = {
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fc2a },
+ { _MMIO(0x2774), 0x0000bf00 },
+ { _MMIO(0x2778), 0x0007fc6a },
+ { _MMIO(0x277c), 0x0000bf00 },
+ { _MMIO(0x2780), 0x0007fc92 },
+ { _MMIO(0x2784), 0x0000bf00 },
+ { _MMIO(0x2788), 0x0007fca2 },
+ { _MMIO(0x278c), 0x0000bf00 },
+ { _MMIO(0x2790), 0x0007fc32 },
+ { _MMIO(0x2794), 0x0000bf00 },
+ { _MMIO(0x2798), 0x0007fc9a },
+ { _MMIO(0x279c), 0x0000bf00 },
+ { _MMIO(0x27a0), 0x0007fe6a },
+ { _MMIO(0x27a4), 0x0000bf00 },
+ { _MMIO(0x27a8), 0x0007fe7a },
+ { _MMIO(0x27ac), 0x0000bf00 },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extended[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00778008 },
+ { _MMIO(0xe45c), 0x00088078 },
+ { _MMIO(0xe55c), 0x00808708 },
+ { _MMIO(0xe65c), 0x00a08908 },
+};
+
+static const struct i915_oa_reg mux_config_compute_extended[] = {
+ { _MMIO(0x9888), 0x106c00e0 },
+ { _MMIO(0x9888), 0x141c8160 },
+ { _MMIO(0x9888), 0x161c8015 },
+ { _MMIO(0x9888), 0x181c0120 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4eaaa0 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0e6c0b01 },
+ { _MMIO(0x9888), 0x006c0200 },
+ { _MMIO(0x9888), 0x026c000c },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x001c0041 },
+ { _MMIO(0x9888), 0x061c4200 },
+ { _MMIO(0x9888), 0x081c4443 },
+ { _MMIO(0x9888), 0x0a1c4645 },
+ { _MMIO(0x9888), 0x0c1c7647 },
+ { _MMIO(0x9888), 0x041c7357 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x101c0000 },
+ { _MMIO(0x9888), 0x1a1c0000 },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4caa2a },
+ { _MMIO(0x9888), 0x0c4c02aa },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x000da000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x0c0f5400 },
+ { _MMIO(0x9888), 0x0e0f5515 },
+ { _MMIO(0x9888), 0x100f0155 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x11907fff },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900040 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900802 },
+ { _MMIO(0x9888), 0x47900842 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900842 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x43900800 },
+ { _MMIO(0x9888), 0x53900000 },
+};
+
+static int
+get_compute_extended_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_extended;
+ lens[n] = ARRAY_SIZE(mux_config_compute_extended);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = {
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2770), 0x0007fffa },
+ { _MMIO(0x2774), 0x0000fefe },
+ { _MMIO(0x2778), 0x0007fffa },
+ { _MMIO(0x277c), 0x0000fefd },
+ { _MMIO(0x2790), 0x0007fffa },
+ { _MMIO(0x2794), 0x0000fbef },
+ { _MMIO(0x2798), 0x0007fffa },
+ { _MMIO(0x279c), 0x0000fbdf },
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00000003 },
+ { _MMIO(0xe658), 0x00002001 },
+ { _MMIO(0xe758), 0x00101100 },
+ { _MMIO(0xe45c), 0x00201200 },
+ { _MMIO(0xe55c), 0x00301300 },
+ { _MMIO(0xe65c), 0x00401400 },
+};
+
+static const struct i915_oa_reg mux_config_compute_l3_cache[] = {
+ { _MMIO(0x9888), 0x166c0760 },
+ { _MMIO(0x9888), 0x1593001e },
+ { _MMIO(0x9888), 0x3f900003 },
+ { _MMIO(0x9888), 0x004e8000 },
+ { _MMIO(0x9888), 0x0e4e8000 },
+ { _MMIO(0x9888), 0x184e8000 },
+ { _MMIO(0x9888), 0x1a4e8020 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x006c0051 },
+ { _MMIO(0x9888), 0x066c5000 },
+ { _MMIO(0x9888), 0x086c5c5d },
+ { _MMIO(0x9888), 0x0e6c5e5f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x186c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x001b4000 },
+ { _MMIO(0x9888), 0x061b8000 },
+ { _MMIO(0x9888), 0x081bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x101c8000 },
+ { _MMIO(0x9888), 0x1a1ce000 },
+ { _MMIO(0x9888), 0x1c1c0030 },
+ { _MMIO(0x9888), 0x004c8000 },
+ { _MMIO(0x9888), 0x0a4c2a00 },
+ { _MMIO(0x9888), 0x0c4c0280 },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f1500 },
+ { _MMIO(0x9888), 0x100f0140 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162c0a00 },
+ { _MMIO(0x9888), 0x182c00a0 },
+ { _MMIO(0x9888), 0x03933300 },
+ { _MMIO(0x9888), 0x05930032 },
+ { _MMIO(0x9888), 0x11930000 },
+ { _MMIO(0x9888), 0x1b930000 },
+ { _MMIO(0x9888), 0x1d900157 },
+ { _MMIO(0x9888), 0x1f900158 },
+ { _MMIO(0x9888), 0x35900000 },
+ { _MMIO(0x9888), 0x19908000 },
+ { _MMIO(0x9888), 0x1b908000 },
+ { _MMIO(0x9888), 0x1190030f },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900000 },
+ { _MMIO(0x9888), 0x55900000 },
+ { _MMIO(0x9888), 0x45900021 },
+ { _MMIO(0x9888), 0x47900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x4b900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x53904444 },
+ { _MMIO(0x9888), 0x43900000 },
+};
+
+static int
+get_compute_l3_cache_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_l3_cache;
+ lens[n] = ARRAY_SIZE(mux_config_compute_l3_cache);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x10800000 },
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000fdff },
+};
+
+static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_hdc_and_sf[] = {
+ { _MMIO(0x9888), 0x104f0232 },
+ { _MMIO(0x9888), 0x124f4640 },
+ { _MMIO(0x9888), 0x106c0232 },
+ { _MMIO(0x9888), 0x11834400 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x004f1880 },
+ { _MMIO(0x9888), 0x024f08bb },
+ { _MMIO(0x9888), 0x044f001b },
+ { _MMIO(0x9888), 0x046c0100 },
+ { _MMIO(0x9888), 0x066c000b },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x041b8000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x005b8000 },
+ { _MMIO(0x9888), 0x025bc000 },
+ { _MMIO(0x9888), 0x045b4000 },
+ { _MMIO(0x9888), 0x125c8000 },
+ { _MMIO(0x9888), 0x145c8000 },
+ { _MMIO(0x9888), 0x165c8000 },
+ { _MMIO(0x9888), 0x185c8000 },
+ { _MMIO(0x9888), 0x0a4c00a0 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x022cc000 },
+ { _MMIO(0x9888), 0x042cc000 },
+ { _MMIO(0x9888), 0x062cc000 },
+ { _MMIO(0x9888), 0x082cc000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x0f828000 },
+ { _MMIO(0x9888), 0x0f8305c0 },
+ { _MMIO(0x9888), 0x09830000 },
+ { _MMIO(0x9888), 0x07830000 },
+ { _MMIO(0x9888), 0x1d950080 },
+ { _MMIO(0x9888), 0x13928000 },
+ { _MMIO(0x9888), 0x0f988000 },
+ { _MMIO(0x9888), 0x31904000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x4b900040 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_hdc_and_sf_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_hdc_and_sf;
+ lens[n] = ARRAY_SIZE(mux_config_hdc_and_sf);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00014002 },
+ { _MMIO(0x277c), 0x0000c3ff },
+ { _MMIO(0x2780), 0x00010002 },
+ { _MMIO(0x2784), 0x0000c7ff },
+ { _MMIO(0x2788), 0x00004002 },
+ { _MMIO(0x278c), 0x0000d3ff },
+ { _MMIO(0x2790), 0x00100700 },
+ { _MMIO(0x2794), 0x0000ff1f },
+ { _MMIO(0x2798), 0x00001402 },
+ { _MMIO(0x279c), 0x0000fc3f },
+ { _MMIO(0x27a0), 0x00001002 },
+ { _MMIO(0x27a4), 0x0000fc7f },
+ { _MMIO(0x27a8), 0x00000402 },
+ { _MMIO(0x27ac), 0x0000fd3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_1[] = {
+ { _MMIO(0x9888), 0x126c7b40 },
+ { _MMIO(0x9888), 0x166c0020 },
+ { _MMIO(0x9888), 0x0a603444 },
+ { _MMIO(0x9888), 0x0a613400 },
+ { _MMIO(0x9888), 0x1a4ea800 },
+ { _MMIO(0x9888), 0x1c4e0002 },
+ { _MMIO(0x9888), 0x024e8000 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x0c6c5327 },
+ { _MMIO(0x9888), 0x0e6c5425 },
+ { _MMIO(0x9888), 0x006c2a00 },
+ { _MMIO(0x9888), 0x026c285b },
+ { _MMIO(0x9888), 0x046c005c },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1c6c0000 },
+ { _MMIO(0x9888), 0x1e6c0000 },
+ { _MMIO(0x9888), 0x1a6c0800 },
+ { _MMIO(0x9888), 0x0c1bc000 },
+ { _MMIO(0x9888), 0x0e1bc000 },
+ { _MMIO(0x9888), 0x001b8000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x1c1c003c },
+ { _MMIO(0x9888), 0x121c8000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x10600000 },
+ { _MMIO(0x9888), 0x04600000 },
+ { _MMIO(0x9888), 0x0c610044 },
+ { _MMIO(0x9888), 0x10610000 },
+ { _MMIO(0x9888), 0x06610000 },
+ { _MMIO(0x9888), 0x0c4c02a8 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0154 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x182c00aa },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190ffc0 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900420 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900021 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900400 },
+ { _MMIO(0x9888), 0x43900421 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static int
+get_l3_1_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_1;
+ lens[n] = ARRAY_SIZE(mux_config_l3_1);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_2[] = {
+ { _MMIO(0x9888), 0x126c02e0 },
+ { _MMIO(0x9888), 0x146c0001 },
+ { _MMIO(0x9888), 0x0a623400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x064f4000 },
+ { _MMIO(0x9888), 0x026c3324 },
+ { _MMIO(0x9888), 0x046c3422 },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c0000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c0800 },
+ { _MMIO(0x9888), 0x065b4000 },
+ { _MMIO(0x9888), 0x1a5c1000 },
+ { _MMIO(0x9888), 0x06614000 },
+ { _MMIO(0x9888), 0x0c620044 },
+ { _MMIO(0x9888), 0x10620000 },
+ { _MMIO(0x9888), 0x06620000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c002a },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2cc000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_l3_2_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_2;
+ lens[n] = ARRAY_SIZE(mux_config_l3_2);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_l3_3[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00100070 },
+ { _MMIO(0x2774), 0x0000fff1 },
+ { _MMIO(0x2778), 0x00028002 },
+ { _MMIO(0x277c), 0x000087ff },
+ { _MMIO(0x2780), 0x00020002 },
+ { _MMIO(0x2784), 0x00008fff },
+ { _MMIO(0x2788), 0x00008002 },
+ { _MMIO(0x278c), 0x0000a7ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_l3_3[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_l3_3[] = {
+ { _MMIO(0x9888), 0x126c4e80 },
+ { _MMIO(0x9888), 0x146c0000 },
+ { _MMIO(0x9888), 0x0a633400 },
+ { _MMIO(0x9888), 0x044e8000 },
+ { _MMIO(0x9888), 0x064e8000 },
+ { _MMIO(0x9888), 0x084e8000 },
+ { _MMIO(0x9888), 0x0a4e8000 },
+ { _MMIO(0x9888), 0x0c4e8000 },
+ { _MMIO(0x9888), 0x026c3321 },
+ { _MMIO(0x9888), 0x046c342f },
+ { _MMIO(0x9888), 0x106c0000 },
+ { _MMIO(0x9888), 0x1a6c2000 },
+ { _MMIO(0x9888), 0x021bc000 },
+ { _MMIO(0x9888), 0x041bc000 },
+ { _MMIO(0x9888), 0x061b4000 },
+ { _MMIO(0x9888), 0x141c8000 },
+ { _MMIO(0x9888), 0x161c8000 },
+ { _MMIO(0x9888), 0x181c8000 },
+ { _MMIO(0x9888), 0x1a1c1800 },
+ { _MMIO(0x9888), 0x06604000 },
+ { _MMIO(0x9888), 0x0c630044 },
+ { _MMIO(0x9888), 0x10630000 },
+ { _MMIO(0x9888), 0x06630000 },
+ { _MMIO(0x9888), 0x084c8000 },
+ { _MMIO(0x9888), 0x0a4c00aa },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f4000 },
+ { _MMIO(0x9888), 0x0e0f0055 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190f800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900002 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_l3_3_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_l3_3;
+ lens[n] = ARRAY_SIZE(mux_config_l3_3);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x30800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x0000efff },
+ { _MMIO(0x2778), 0x00006000 },
+ { _MMIO(0x277c), 0x0000f3ff },
+};
+
+static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = {
+ { _MMIO(0x9888), 0x102f3800 },
+ { _MMIO(0x9888), 0x144d0500 },
+ { _MMIO(0x9888), 0x120d03c0 },
+ { _MMIO(0x9888), 0x140d03cf },
+ { _MMIO(0x9888), 0x0c0f0004 },
+ { _MMIO(0x9888), 0x0c4e4000 },
+ { _MMIO(0x9888), 0x042f0480 },
+ { _MMIO(0x9888), 0x082f0000 },
+ { _MMIO(0x9888), 0x022f0000 },
+ { _MMIO(0x9888), 0x0a4c0090 },
+ { _MMIO(0x9888), 0x064d0027 },
+ { _MMIO(0x9888), 0x004d0000 },
+ { _MMIO(0x9888), 0x000d0d40 },
+ { _MMIO(0x9888), 0x020d803f },
+ { _MMIO(0x9888), 0x040d8023 },
+ { _MMIO(0x9888), 0x100d0000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x020f0010 },
+ { _MMIO(0x9888), 0x000f0000 },
+ { _MMIO(0x9888), 0x0e0f0050 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41901400 },
+ { _MMIO(0x9888), 0x43901485 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900001 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_rasterizer_and_pixel_backend_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_rasterizer_and_pixel_backend;
+ lens[n] = ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_sampler[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x70800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+ { _MMIO(0x2770), 0x0000c000 },
+ { _MMIO(0x2774), 0x0000e7ff },
+ { _MMIO(0x2778), 0x00003000 },
+ { _MMIO(0x277c), 0x0000f9ff },
+ { _MMIO(0x2780), 0x00000c00 },
+ { _MMIO(0x2784), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_sampler[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_sampler[] = {
+ { _MMIO(0x9888), 0x14152c00 },
+ { _MMIO(0x9888), 0x16150005 },
+ { _MMIO(0x9888), 0x121600a0 },
+ { _MMIO(0x9888), 0x14352c00 },
+ { _MMIO(0x9888), 0x16350005 },
+ { _MMIO(0x9888), 0x123600a0 },
+ { _MMIO(0x9888), 0x14552c00 },
+ { _MMIO(0x9888), 0x16550005 },
+ { _MMIO(0x9888), 0x125600a0 },
+ { _MMIO(0x9888), 0x062f6000 },
+ { _MMIO(0x9888), 0x022f2000 },
+ { _MMIO(0x9888), 0x0c4c0050 },
+ { _MMIO(0x9888), 0x0a4c0010 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f0350 },
+ { _MMIO(0x9888), 0x0c0fb000 },
+ { _MMIO(0x9888), 0x0e0f00da },
+ { _MMIO(0x9888), 0x182c0028 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x022dc000 },
+ { _MMIO(0x9888), 0x042d4000 },
+ { _MMIO(0x9888), 0x0c138000 },
+ { _MMIO(0x9888), 0x0e132000 },
+ { _MMIO(0x9888), 0x0413c000 },
+ { _MMIO(0x9888), 0x1c140018 },
+ { _MMIO(0x9888), 0x0c157000 },
+ { _MMIO(0x9888), 0x0e150078 },
+ { _MMIO(0x9888), 0x10150000 },
+ { _MMIO(0x9888), 0x04162180 },
+ { _MMIO(0x9888), 0x02160000 },
+ { _MMIO(0x9888), 0x04174000 },
+ { _MMIO(0x9888), 0x0233a000 },
+ { _MMIO(0x9888), 0x04333000 },
+ { _MMIO(0x9888), 0x14348000 },
+ { _MMIO(0x9888), 0x16348000 },
+ { _MMIO(0x9888), 0x02357870 },
+ { _MMIO(0x9888), 0x10350000 },
+ { _MMIO(0x9888), 0x04360043 },
+ { _MMIO(0x9888), 0x02360000 },
+ { _MMIO(0x9888), 0x04371000 },
+ { _MMIO(0x9888), 0x0e538000 },
+ { _MMIO(0x9888), 0x00538000 },
+ { _MMIO(0x9888), 0x06533000 },
+ { _MMIO(0x9888), 0x1c540020 },
+ { _MMIO(0x9888), 0x12548000 },
+ { _MMIO(0x9888), 0x0e557000 },
+ { _MMIO(0x9888), 0x00557800 },
+ { _MMIO(0x9888), 0x10550000 },
+ { _MMIO(0x9888), 0x06560043 },
+ { _MMIO(0x9888), 0x02560000 },
+ { _MMIO(0x9888), 0x06571000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900060 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900842 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900060 },
+};
+
+static int
+get_sampler_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_sampler;
+ lens[n] = ARRAY_SIZE(mux_config_sampler);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_1[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00000002 },
+ { _MMIO(0x2774), 0x00007fff },
+ { _MMIO(0x2778), 0x00000000 },
+ { _MMIO(0x277c), 0x00009fff },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000efff },
+ { _MMIO(0x2788), 0x00000000 },
+ { _MMIO(0x278c), 0x0000f3ff },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000fdff },
+ { _MMIO(0x2798), 0x00000000 },
+ { _MMIO(0x279c), 0x0000fe7f },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_1[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_1[] = {
+ { _MMIO(0x9888), 0x12120000 },
+ { _MMIO(0x9888), 0x12320000 },
+ { _MMIO(0x9888), 0x12520000 },
+ { _MMIO(0x9888), 0x002f8000 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0015 },
+ { _MMIO(0x9888), 0x0c0d8000 },
+ { _MMIO(0x9888), 0x0e0da000 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x100f03a0 },
+ { _MMIO(0x9888), 0x0c0ff000 },
+ { _MMIO(0x9888), 0x0e0f0095 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x0c2d8000 },
+ { _MMIO(0x9888), 0x0e2d4000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x02108000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x02118000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x02121880 },
+ { _MMIO(0x9888), 0x041219b5 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x02134000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x0c308000 },
+ { _MMIO(0x9888), 0x0e304000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x0c318000 },
+ { _MMIO(0x9888), 0x0e314000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x0c321a80 },
+ { _MMIO(0x9888), 0x0e320033 },
+ { _MMIO(0x9888), 0x06320031 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x0c334000 },
+ { _MMIO(0x9888), 0x0e331000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0e508000 },
+ { _MMIO(0x9888), 0x00508000 },
+ { _MMIO(0x9888), 0x02504000 },
+ { _MMIO(0x9888), 0x0e518000 },
+ { _MMIO(0x9888), 0x00518000 },
+ { _MMIO(0x9888), 0x02514000 },
+ { _MMIO(0x9888), 0x0e521880 },
+ { _MMIO(0x9888), 0x00521a80 },
+ { _MMIO(0x9888), 0x02520033 },
+ { _MMIO(0x9888), 0x0e534000 },
+ { _MMIO(0x9888), 0x00534000 },
+ { _MMIO(0x9888), 0x02531000 },
+ { _MMIO(0x9888), 0x1190ff80 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900800 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+ { _MMIO(0x9888), 0x4b900062 },
+ { _MMIO(0x9888), 0x59900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900003 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+};
+
+static int
+get_tdl_1_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_tdl_1;
+ lens[n] = ARRAY_SIZE(mux_config_tdl_1);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_tdl_2[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0x00800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x00800000 },
+};
+
+static const struct i915_oa_reg flex_eu_config_tdl_2[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00010003 },
+ { _MMIO(0xe658), 0x00012011 },
+ { _MMIO(0xe758), 0x00015014 },
+ { _MMIO(0xe45c), 0x00051050 },
+ { _MMIO(0xe55c), 0x00053052 },
+ { _MMIO(0xe65c), 0x00055054 },
+};
+
+static const struct i915_oa_reg mux_config_tdl_2[] = {
+ { _MMIO(0x9888), 0x12124d60 },
+ { _MMIO(0x9888), 0x12322e60 },
+ { _MMIO(0x9888), 0x12524d60 },
+ { _MMIO(0x9888), 0x022f3000 },
+ { _MMIO(0x9888), 0x0a4c0014 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0fe000 },
+ { _MMIO(0x9888), 0x0e0f0097 },
+ { _MMIO(0x9888), 0x082c8000 },
+ { _MMIO(0x9888), 0x0a2c8000 },
+ { _MMIO(0x9888), 0x002d8000 },
+ { _MMIO(0x9888), 0x062d4000 },
+ { _MMIO(0x9888), 0x0410c000 },
+ { _MMIO(0x9888), 0x0411c000 },
+ { _MMIO(0x9888), 0x04121fb7 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x04135000 },
+ { _MMIO(0x9888), 0x00308000 },
+ { _MMIO(0x9888), 0x06304000 },
+ { _MMIO(0x9888), 0x00318000 },
+ { _MMIO(0x9888), 0x06314000 },
+ { _MMIO(0x9888), 0x00321b80 },
+ { _MMIO(0x9888), 0x0632003f },
+ { _MMIO(0x9888), 0x00334000 },
+ { _MMIO(0x9888), 0x06331000 },
+ { _MMIO(0x9888), 0x0250c000 },
+ { _MMIO(0x9888), 0x0251c000 },
+ { _MMIO(0x9888), 0x02521fb7 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x02535000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900800 },
+ { _MMIO(0x9888), 0x43900063 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900040 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_tdl_2_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_tdl_2;
+ lens[n] = ARRAY_SIZE(mux_config_tdl_2);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg flex_eu_config_compute_extra[] = {
+};
+
+static const struct i915_oa_reg mux_config_compute_extra[] = {
+ { _MMIO(0x9888), 0x121203e0 },
+ { _MMIO(0x9888), 0x123203e0 },
+ { _MMIO(0x9888), 0x125203e0 },
+ { _MMIO(0x9888), 0x129203e0 },
+ { _MMIO(0x9888), 0x12b203e0 },
+ { _MMIO(0x9888), 0x12d203e0 },
+ { _MMIO(0x9888), 0x024ec000 },
+ { _MMIO(0x9888), 0x044ec000 },
+ { _MMIO(0x9888), 0x064ec000 },
+ { _MMIO(0x9888), 0x022f4000 },
+ { _MMIO(0x9888), 0x084ca000 },
+ { _MMIO(0x9888), 0x0a4c0042 },
+ { _MMIO(0x9888), 0x000d8000 },
+ { _MMIO(0x9888), 0x020da000 },
+ { _MMIO(0x9888), 0x040da000 },
+ { _MMIO(0x9888), 0x060d2000 },
+ { _MMIO(0x9888), 0x0c0f5000 },
+ { _MMIO(0x9888), 0x0e0f006d },
+ { _MMIO(0x9888), 0x022c8000 },
+ { _MMIO(0x9888), 0x042c8000 },
+ { _MMIO(0x9888), 0x062c8000 },
+ { _MMIO(0x9888), 0x0c2c8000 },
+ { _MMIO(0x9888), 0x042d8000 },
+ { _MMIO(0x9888), 0x06104000 },
+ { _MMIO(0x9888), 0x06114000 },
+ { _MMIO(0x9888), 0x06120033 },
+ { _MMIO(0x9888), 0x00120000 },
+ { _MMIO(0x9888), 0x06131000 },
+ { _MMIO(0x9888), 0x04308000 },
+ { _MMIO(0x9888), 0x04318000 },
+ { _MMIO(0x9888), 0x04321980 },
+ { _MMIO(0x9888), 0x00320000 },
+ { _MMIO(0x9888), 0x04334000 },
+ { _MMIO(0x9888), 0x04504000 },
+ { _MMIO(0x9888), 0x04514000 },
+ { _MMIO(0x9888), 0x04520033 },
+ { _MMIO(0x9888), 0x00520000 },
+ { _MMIO(0x9888), 0x04531000 },
+ { _MMIO(0x9888), 0x00af8000 },
+ { _MMIO(0x9888), 0x0acc0001 },
+ { _MMIO(0x9888), 0x008d8000 },
+ { _MMIO(0x9888), 0x028da000 },
+ { _MMIO(0x9888), 0x0c8fb000 },
+ { _MMIO(0x9888), 0x0e8f0001 },
+ { _MMIO(0x9888), 0x06ac8000 },
+ { _MMIO(0x9888), 0x02ad4000 },
+ { _MMIO(0x9888), 0x02908000 },
+ { _MMIO(0x9888), 0x02918000 },
+ { _MMIO(0x9888), 0x02921980 },
+ { _MMIO(0x9888), 0x00920000 },
+ { _MMIO(0x9888), 0x02934000 },
+ { _MMIO(0x9888), 0x02b04000 },
+ { _MMIO(0x9888), 0x02b14000 },
+ { _MMIO(0x9888), 0x02b20033 },
+ { _MMIO(0x9888), 0x00b20000 },
+ { _MMIO(0x9888), 0x02b31000 },
+ { _MMIO(0x9888), 0x00d08000 },
+ { _MMIO(0x9888), 0x00d18000 },
+ { _MMIO(0x9888), 0x00d21980 },
+ { _MMIO(0x9888), 0x00d34000 },
+ { _MMIO(0x9888), 0x1190fc00 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x51900000 },
+ { _MMIO(0x9888), 0x41900c00 },
+ { _MMIO(0x9888), 0x43900002 },
+ { _MMIO(0x9888), 0x53900420 },
+ { _MMIO(0x9888), 0x459000a1 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_compute_extra_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_compute_extra;
+ lens[n] = ARRAY_SIZE(mux_config_compute_extra);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_vme_pipe[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2724), 0x30800000 },
+ { _MMIO(0x2770), 0x00100030 },
+ { _MMIO(0x2774), 0x0000fff9 },
+ { _MMIO(0x2778), 0x00000002 },
+ { _MMIO(0x277c), 0x0000fffc },
+ { _MMIO(0x2780), 0x00000002 },
+ { _MMIO(0x2784), 0x0000fff3 },
+ { _MMIO(0x2788), 0x00100180 },
+ { _MMIO(0x278c), 0x0000ffcf },
+ { _MMIO(0x2790), 0x00000002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00000002 },
+ { _MMIO(0x279c), 0x0000ff3f },
+};
+
+static const struct i915_oa_reg flex_eu_config_vme_pipe[] = {
+ { _MMIO(0xe458), 0x00005004 },
+ { _MMIO(0xe558), 0x00008003 },
+};
+
+static const struct i915_oa_reg mux_config_vme_pipe[] = {
+ { _MMIO(0x9888), 0x141a5800 },
+ { _MMIO(0x9888), 0x161a00c0 },
+ { _MMIO(0x9888), 0x12180240 },
+ { _MMIO(0x9888), 0x14180002 },
+ { _MMIO(0x9888), 0x149a5800 },
+ { _MMIO(0x9888), 0x169a00c0 },
+ { _MMIO(0x9888), 0x12980240 },
+ { _MMIO(0x9888), 0x14980002 },
+ { _MMIO(0x9888), 0x1a4e3fc0 },
+ { _MMIO(0x9888), 0x002f1000 },
+ { _MMIO(0x9888), 0x022f8000 },
+ { _MMIO(0x9888), 0x042f3000 },
+ { _MMIO(0x9888), 0x004c4000 },
+ { _MMIO(0x9888), 0x0a4c9500 },
+ { _MMIO(0x9888), 0x0c4c002a },
+ { _MMIO(0x9888), 0x000d2000 },
+ { _MMIO(0x9888), 0x060d8000 },
+ { _MMIO(0x9888), 0x080da000 },
+ { _MMIO(0x9888), 0x0a0da000 },
+ { _MMIO(0x9888), 0x0c0da000 },
+ { _MMIO(0x9888), 0x0c0f0400 },
+ { _MMIO(0x9888), 0x0e0f5500 },
+ { _MMIO(0x9888), 0x100f0015 },
+ { _MMIO(0x9888), 0x002c8000 },
+ { _MMIO(0x9888), 0x0e2c8000 },
+ { _MMIO(0x9888), 0x162caa00 },
+ { _MMIO(0x9888), 0x182c000a },
+ { _MMIO(0x9888), 0x04193000 },
+ { _MMIO(0x9888), 0x081a28c1 },
+ { _MMIO(0x9888), 0x001a0000 },
+ { _MMIO(0x9888), 0x00133000 },
+ { _MMIO(0x9888), 0x0613c000 },
+ { _MMIO(0x9888), 0x0813f000 },
+ { _MMIO(0x9888), 0x00172000 },
+ { _MMIO(0x9888), 0x06178000 },
+ { _MMIO(0x9888), 0x0817a000 },
+ { _MMIO(0x9888), 0x00180037 },
+ { _MMIO(0x9888), 0x06180940 },
+ { _MMIO(0x9888), 0x08180000 },
+ { _MMIO(0x9888), 0x02180000 },
+ { _MMIO(0x9888), 0x04183000 },
+ { _MMIO(0x9888), 0x04afc000 },
+ { _MMIO(0x9888), 0x06af3000 },
+ { _MMIO(0x9888), 0x0acc4000 },
+ { _MMIO(0x9888), 0x0ccc0015 },
+ { _MMIO(0x9888), 0x0a8da000 },
+ { _MMIO(0x9888), 0x0c8da000 },
+ { _MMIO(0x9888), 0x0e8f4000 },
+ { _MMIO(0x9888), 0x108f0015 },
+ { _MMIO(0x9888), 0x16aca000 },
+ { _MMIO(0x9888), 0x18ac000a },
+ { _MMIO(0x9888), 0x06993000 },
+ { _MMIO(0x9888), 0x0c9a28c1 },
+ { _MMIO(0x9888), 0x009a0000 },
+ { _MMIO(0x9888), 0x0a93f000 },
+ { _MMIO(0x9888), 0x0c93f000 },
+ { _MMIO(0x9888), 0x0a97a000 },
+ { _MMIO(0x9888), 0x0c97a000 },
+ { _MMIO(0x9888), 0x0a980977 },
+ { _MMIO(0x9888), 0x08980000 },
+ { _MMIO(0x9888), 0x04980000 },
+ { _MMIO(0x9888), 0x06983000 },
+ { _MMIO(0x9888), 0x119000ff },
+ { _MMIO(0x9888), 0x51900040 },
+ { _MMIO(0x9888), 0x41900020 },
+ { _MMIO(0x9888), 0x55900004 },
+ { _MMIO(0x9888), 0x45900400 },
+ { _MMIO(0x9888), 0x479008a5 },
+ { _MMIO(0x9888), 0x57900000 },
+ { _MMIO(0x9888), 0x49900002 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_vme_pipe_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_vme_pipe;
+ lens[n] = ARRAY_SIZE(mux_config_vme_pipe);
+ n++;
+
+ return n;
+}
+
+static const struct i915_oa_reg b_counter_config_test_oa[] = {
+ { _MMIO(0x2740), 0x00000000 },
+ { _MMIO(0x2744), 0x00800000 },
+ { _MMIO(0x2714), 0xf0800000 },
+ { _MMIO(0x2710), 0x00000000 },
+ { _MMIO(0x2724), 0xf0800000 },
+ { _MMIO(0x2720), 0x00000000 },
+ { _MMIO(0x2770), 0x00000004 },
+ { _MMIO(0x2774), 0x00000000 },
+ { _MMIO(0x2778), 0x00000003 },
+ { _MMIO(0x277c), 0x00000000 },
+ { _MMIO(0x2780), 0x00000007 },
+ { _MMIO(0x2784), 0x00000000 },
+ { _MMIO(0x2788), 0x00100002 },
+ { _MMIO(0x278c), 0x0000fff7 },
+ { _MMIO(0x2790), 0x00100002 },
+ { _MMIO(0x2794), 0x0000ffcf },
+ { _MMIO(0x2798), 0x00100082 },
+ { _MMIO(0x279c), 0x0000ffef },
+ { _MMIO(0x27a0), 0x001000c2 },
+ { _MMIO(0x27a4), 0x0000ffe7 },
+ { _MMIO(0x27a8), 0x00100001 },
+ { _MMIO(0x27ac), 0x0000ffe7 },
+};
+
+static const struct i915_oa_reg flex_eu_config_test_oa[] = {
+};
+
+static const struct i915_oa_reg mux_config_test_oa[] = {
+ { _MMIO(0x9888), 0x11810000 },
+ { _MMIO(0x9888), 0x07810013 },
+ { _MMIO(0x9888), 0x1f810000 },
+ { _MMIO(0x9888), 0x1d810000 },
+ { _MMIO(0x9888), 0x1b930040 },
+ { _MMIO(0x9888), 0x07e54000 },
+ { _MMIO(0x9888), 0x1f908000 },
+ { _MMIO(0x9888), 0x11900000 },
+ { _MMIO(0x9888), 0x37900000 },
+ { _MMIO(0x9888), 0x53900000 },
+ { _MMIO(0x9888), 0x45900000 },
+ { _MMIO(0x9888), 0x33900000 },
+};
+
+static int
+get_test_oa_mux_config(struct drm_i915_private *dev_priv,
+ const struct i915_oa_reg **regs,
+ int *lens)
+{
+ int n = 0;
+
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs) < 1);
+ BUILD_BUG_ON(ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens) < 1);
+
+ regs[n] = mux_config_test_oa;
+ lens[n] = ARRAY_SIZE(mux_config_test_oa);
+ n++;
+
+ return n;
+}
+
+int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv)
+{
+ dev_priv->perf.oa.n_mux_regs = 0;
+ dev_priv->perf.oa.b_counter_regs = NULL;
+ dev_priv->perf.oa.b_counter_regs_len = 0;
+ dev_priv->perf.oa.flex_regs = NULL;
+ dev_priv->perf.oa.flex_regs_len = 0;
+
+ switch (dev_priv->perf.oa.metrics_set) {
+ case METRIC_SET_ID_RENDER_BASIC:
+ dev_priv->perf.oa.n_mux_regs =
+ get_render_basic_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_basic);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_BASIC:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_basic_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_basic;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_basic);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_basic;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_basic);
+
+ return 0;
+ case METRIC_SET_ID_RENDER_PIPE_PROFILE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_render_pipe_profile_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_render_pipe_profile;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_render_pipe_profile);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_render_pipe_profile;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_render_pipe_profile);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_READS:
+ dev_priv->perf.oa.n_mux_regs =
+ get_memory_reads_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_reads;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_reads);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_reads;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_reads);
+
+ return 0;
+ case METRIC_SET_ID_MEMORY_WRITES:
+ dev_priv->perf.oa.n_mux_regs =
+ get_memory_writes_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_memory_writes;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_memory_writes);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_memory_writes;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_memory_writes);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTENDED:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_extended_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extended;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extended);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extended;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extended);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_L3_CACHE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_l3_cache_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_L3_CACHE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_l3_cache;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_l3_cache);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_l3_cache;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_l3_cache);
+
+ return 0;
+ case METRIC_SET_ID_HDC_AND_SF:
+ dev_priv->perf.oa.n_mux_regs =
+ get_hdc_and_sf_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"HDC_AND_SF\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_hdc_and_sf;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_hdc_and_sf);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_hdc_and_sf;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_hdc_and_sf);
+
+ return 0;
+ case METRIC_SET_ID_L3_1:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_1_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_1\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_1);
+
+ return 0;
+ case METRIC_SET_ID_L3_2:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_2_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_2\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_2);
+
+ return 0;
+ case METRIC_SET_ID_L3_3:
+ dev_priv->perf.oa.n_mux_regs =
+ get_l3_3_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"L3_3\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_l3_3;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_l3_3);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_l3_3;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_l3_3);
+
+ return 0;
+ case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND:
+ dev_priv->perf.oa.n_mux_regs =
+ get_rasterizer_and_pixel_backend_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"RASTERIZER_AND_PIXEL_BACKEND\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_rasterizer_and_pixel_backend;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend);
+
+ return 0;
+ case METRIC_SET_ID_SAMPLER:
+ dev_priv->perf.oa.n_mux_regs =
+ get_sampler_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"SAMPLER\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_sampler;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_sampler);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_sampler;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_sampler);
+
+ return 0;
+ case METRIC_SET_ID_TDL_1:
+ dev_priv->perf.oa.n_mux_regs =
+ get_tdl_1_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_1\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_1;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_1);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_1;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_1);
+
+ return 0;
+ case METRIC_SET_ID_TDL_2:
+ dev_priv->perf.oa.n_mux_regs =
+ get_tdl_2_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TDL_2\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_tdl_2;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_tdl_2);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_tdl_2;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_tdl_2);
+
+ return 0;
+ case METRIC_SET_ID_COMPUTE_EXTRA:
+ dev_priv->perf.oa.n_mux_regs =
+ get_compute_extra_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTRA\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_compute_extra;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_compute_extra);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_compute_extra;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_compute_extra);
+
+ return 0;
+ case METRIC_SET_ID_VME_PIPE:
+ dev_priv->perf.oa.n_mux_regs =
+ get_vme_pipe_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"VME_PIPE\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_vme_pipe;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_vme_pipe);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_vme_pipe;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_vme_pipe);
+
+ return 0;
+ case METRIC_SET_ID_TEST_OA:
+ dev_priv->perf.oa.n_mux_regs =
+ get_test_oa_mux_config(dev_priv,
+ dev_priv->perf.oa.mux_regs,
+ dev_priv->perf.oa.mux_regs_lens);
+ if (dev_priv->perf.oa.n_mux_regs == 0) {
+ DRM_DEBUG_DRIVER("No suitable MUX config for \"TEST_OA\" metric set\n");
+
+ /* EINVAL because *_register_sysfs already checked this
+ * and so it wouldn't have been advertised to userspace and
+ * so shouldn't have been requested
+ */
+ return -EINVAL;
+ }
+
+ dev_priv->perf.oa.b_counter_regs =
+ b_counter_config_test_oa;
+ dev_priv->perf.oa.b_counter_regs_len =
+ ARRAY_SIZE(b_counter_config_test_oa);
+
+ dev_priv->perf.oa.flex_regs =
+ flex_eu_config_test_oa;
+ dev_priv->perf.oa.flex_regs_len =
+ ARRAY_SIZE(flex_eu_config_test_oa);
+
+ return 0;
+ default:
+ return -ENODEV;
+ }
+}
+
+static ssize_t
+show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC);
+}
+
+static struct device_attribute dev_attr_render_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_basic[] = {
+ &dev_attr_render_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_basic = {
+ .name = "0286c920-2f6d-493b-b22d-7a5280df43de",
+ .attrs = attrs_render_basic,
+};
+
+static ssize_t
+show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC);
+}
+
+static struct device_attribute dev_attr_compute_basic_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_basic_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_basic[] = {
+ &dev_attr_compute_basic_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_basic = {
+ .name = "9823aaa1-b06f-40ce-884b-cd798c79f0c2",
+ .attrs = attrs_compute_basic,
+};
+
+static ssize_t
+show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE);
+}
+
+static struct device_attribute dev_attr_render_pipe_profile_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_render_pipe_profile_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_render_pipe_profile[] = {
+ &dev_attr_render_pipe_profile_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_render_pipe_profile = {
+ .name = "c7c735f3-ce58-45cf-aa04-30b183f1faff",
+ .attrs = attrs_render_pipe_profile,
+};
+
+static ssize_t
+show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS);
+}
+
+static struct device_attribute dev_attr_memory_reads_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_reads_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_reads[] = {
+ &dev_attr_memory_reads_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_reads = {
+ .name = "96ec2219-040b-428a-856a-6bc03363a057",
+ .attrs = attrs_memory_reads,
+};
+
+static ssize_t
+show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES);
+}
+
+static struct device_attribute dev_attr_memory_writes_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_memory_writes_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_memory_writes[] = {
+ &dev_attr_memory_writes_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_memory_writes = {
+ .name = "03372b64-4996-4d3b-aa18-790e75eeb9c2",
+ .attrs = attrs_memory_writes,
+};
+
+static ssize_t
+show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED);
+}
+
+static struct device_attribute dev_attr_compute_extended_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extended_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extended[] = {
+ &dev_attr_compute_extended_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extended = {
+ .name = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150",
+ .attrs = attrs_compute_extended,
+};
+
+static ssize_t
+show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE);
+}
+
+static struct device_attribute dev_attr_compute_l3_cache_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_l3_cache_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_l3_cache[] = {
+ &dev_attr_compute_l3_cache_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_l3_cache = {
+ .name = "2ce0911a-27fc-4887-96f0-11084fa807c3",
+ .attrs = attrs_compute_l3_cache,
+};
+
+static ssize_t
+show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF);
+}
+
+static struct device_attribute dev_attr_hdc_and_sf_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_hdc_and_sf_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_hdc_and_sf[] = {
+ &dev_attr_hdc_and_sf_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_hdc_and_sf = {
+ .name = "546c4c1d-99b8-42fb-a107-5aaabb5314a8",
+ .attrs = attrs_hdc_and_sf,
+};
+
+static ssize_t
+show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1);
+}
+
+static struct device_attribute dev_attr_l3_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_1[] = {
+ &dev_attr_l3_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_1 = {
+ .name = "4e93d156-9b39-4268-8544-a8e0480806d7",
+ .attrs = attrs_l3_1,
+};
+
+static ssize_t
+show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2);
+}
+
+static struct device_attribute dev_attr_l3_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_2[] = {
+ &dev_attr_l3_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_2 = {
+ .name = "de1bec86-ca92-4b43-89fa-147653221cc0",
+ .attrs = attrs_l3_2,
+};
+
+static ssize_t
+show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3);
+}
+
+static struct device_attribute dev_attr_l3_3_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_l3_3_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_l3_3[] = {
+ &dev_attr_l3_3_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_l3_3 = {
+ .name = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef",
+ .attrs = attrs_l3_3,
+};
+
+static ssize_t
+show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND);
+}
+
+static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_rasterizer_and_pixel_backend_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_rasterizer_and_pixel_backend[] = {
+ &dev_attr_rasterizer_and_pixel_backend_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_rasterizer_and_pixel_backend = {
+ .name = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281",
+ .attrs = attrs_rasterizer_and_pixel_backend,
+};
+
+static ssize_t
+show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER);
+}
+
+static struct device_attribute dev_attr_sampler_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_sampler_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_sampler[] = {
+ &dev_attr_sampler_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_sampler = {
+ .name = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda",
+ .attrs = attrs_sampler,
+};
+
+static ssize_t
+show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1);
+}
+
+static struct device_attribute dev_attr_tdl_1_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_1_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_1[] = {
+ &dev_attr_tdl_1_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_1 = {
+ .name = "469a05e5-e299-46f7-9598-7b05f3c34991",
+ .attrs = attrs_tdl_1,
+};
+
+static ssize_t
+show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2);
+}
+
+static struct device_attribute dev_attr_tdl_2_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_tdl_2_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_tdl_2[] = {
+ &dev_attr_tdl_2_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_tdl_2 = {
+ .name = "52f925c6-786a-4ec6-86ce-cba85c83453a",
+ .attrs = attrs_tdl_2,
+};
+
+static ssize_t
+show_compute_extra_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTRA);
+}
+
+static struct device_attribute dev_attr_compute_extra_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_compute_extra_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_compute_extra[] = {
+ &dev_attr_compute_extra_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_compute_extra = {
+ .name = "efc497ac-884e-4ee4-a4a8-15fba22aaf21",
+ .attrs = attrs_compute_extra,
+};
+
+static ssize_t
+show_vme_pipe_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_VME_PIPE);
+}
+
+static struct device_attribute dev_attr_vme_pipe_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_vme_pipe_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_vme_pipe[] = {
+ &dev_attr_vme_pipe_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_vme_pipe = {
+ .name = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917",
+ .attrs = attrs_vme_pipe,
+};
+
+static ssize_t
+show_test_oa_id(struct device *kdev, struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", METRIC_SET_ID_TEST_OA);
+}
+
+static struct device_attribute dev_attr_test_oa_id = {
+ .attr = { .name = "id", .mode = 0444 },
+ .show = show_test_oa_id,
+ .store = NULL,
+};
+
+static struct attribute *attrs_test_oa[] = {
+ &dev_attr_test_oa_id.attr,
+ NULL,
+};
+
+static struct attribute_group group_test_oa = {
+ .name = "f1792f32-6db2-4b50-b4b2-557128f1688d",
+ .attrs = attrs_test_oa,
+};
+
+int
+i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv)
+{
+ const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
+ int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
+ int ret = 0;
+
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (ret)
+ goto error_render_basic;
+ }
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (ret)
+ goto error_compute_basic;
+ }
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (ret)
+ goto error_render_pipe_profile;
+ }
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (ret)
+ goto error_memory_reads;
+ }
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (ret)
+ goto error_memory_writes;
+ }
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (ret)
+ goto error_compute_extended;
+ }
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (ret)
+ goto error_compute_l3_cache;
+ }
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (ret)
+ goto error_hdc_and_sf;
+ }
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (ret)
+ goto error_l3_1;
+ }
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (ret)
+ goto error_l3_2;
+ }
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (ret)
+ goto error_l3_3;
+ }
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (ret)
+ goto error_rasterizer_and_pixel_backend;
+ }
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (ret)
+ goto error_sampler;
+ }
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (ret)
+ goto error_tdl_1;
+ }
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (ret)
+ goto error_tdl_2;
+ }
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (ret)
+ goto error_compute_extra;
+ }
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (ret)
+ goto error_vme_pipe;
+ }
+ if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens)) {
+ ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+ if (ret)
+ goto error_test_oa;
+ }
+
+ return 0;
+
+error_test_oa:
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+error_vme_pipe:
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+error_compute_extra:
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+error_tdl_2:
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+error_tdl_1:
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+error_sampler:
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+error_rasterizer_and_pixel_backend:
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+error_l3_3:
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+error_l3_2:
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+error_l3_1:
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+error_hdc_and_sf:
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+error_compute_l3_cache:
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+error_compute_extended:
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+error_memory_writes:
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+error_memory_reads:
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+error_render_pipe_profile:
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+error_compute_basic:
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+error_render_basic:
+ return ret;
+}
+
+void
+i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv)
+{
+ const struct i915_oa_reg *mux_regs[ARRAY_SIZE(dev_priv->perf.oa.mux_regs)];
+ int mux_lens[ARRAY_SIZE(dev_priv->perf.oa.mux_regs_lens)];
+
+ if (get_render_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic);
+ if (get_compute_basic_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic);
+ if (get_render_pipe_profile_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile);
+ if (get_memory_reads_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads);
+ if (get_memory_writes_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes);
+ if (get_compute_extended_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended);
+ if (get_compute_l3_cache_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache);
+ if (get_hdc_and_sf_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf);
+ if (get_l3_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1);
+ if (get_l3_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2);
+ if (get_l3_3_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3);
+ if (get_rasterizer_and_pixel_backend_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend);
+ if (get_sampler_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler);
+ if (get_tdl_1_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1);
+ if (get_tdl_2_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2);
+ if (get_compute_extra_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extra);
+ if (get_vme_pipe_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_vme_pipe);
+ if (get_test_oa_mux_config(dev_priv, mux_regs, mux_lens))
+ sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_test_oa);
+}
diff --git a/drivers/gpu/drm/i915/i915_oa_kblgt3.h b/drivers/gpu/drm/i915/i915_oa_kblgt3.h
new file mode 100644
index 000000000000..10ccccb43a1d
--- /dev/null
+++ b/drivers/gpu/drm/i915/i915_oa_kblgt3.h
@@ -0,0 +1,38 @@
+/*
+ * Autogenerated file, DO NOT EDIT manually!
+ *
+ * Copyright (c) 2015 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __I915_OA_KBLGT3_H__
+#define __I915_OA_KBLGT3_H__
+
+extern int i915_oa_n_builtin_metric_sets_kblgt3;
+
+extern int i915_oa_select_metric_set_kblgt3(struct drm_i915_private *dev_priv);
+
+extern int i915_perf_register_sysfs_kblgt3(struct drm_i915_private *dev_priv);
+
+extern void i915_perf_unregister_sysfs_kblgt3(struct drm_i915_private *dev_priv);
+
+#endif
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index b262a005aa54..a388e26c8a69 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -202,6 +202,8 @@
#include "i915_oa_sklgt3.h"
#include "i915_oa_sklgt4.h"
#include "i915_oa_bxt.h"
+#include "i915_oa_kblgt2.h"
+#include "i915_oa_kblgt3.h"
/* HW requires this to be a power of two, between 128k and 16M, though driver
* is currently generally designed assuming the largest 16M size is used such
@@ -1791,7 +1793,8 @@ static int gen8_enable_metric_set(struct drm_i915_private *dev_priv)
* be read back from automatically triggered reports, as part of the
* RPT_ID field.
*/
- if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv)) {
+ if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+ IS_KABYLAKE(dev_priv)) {
I915_WRITE(GEN8_OA_DEBUG,
_MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
@@ -2912,6 +2915,15 @@ void i915_perf_register(struct drm_i915_private *dev_priv)
} else if (IS_BROXTON(dev_priv)) {
if (i915_perf_register_sysfs_bxt(dev_priv))
goto sysfs_error;
+ } else if (IS_KABYLAKE(dev_priv)) {
+ if (IS_KBL_GT2(dev_priv)) {
+ if (i915_perf_register_sysfs_kblgt2(dev_priv))
+ goto sysfs_error;
+ } else if (IS_KBL_GT3(dev_priv)) {
+ if (i915_perf_register_sysfs_kblgt3(dev_priv))
+ goto sysfs_error;
+ } else
+ goto sysfs_error;
}
goto exit;
@@ -2953,6 +2965,12 @@ void i915_perf_unregister(struct drm_i915_private *dev_priv)
i915_perf_unregister_sysfs_sklgt4(dev_priv);
} else if (IS_BROXTON(dev_priv))
i915_perf_unregister_sysfs_bxt(dev_priv);
+ else if (IS_KABYLAKE(dev_priv)) {
+ if (IS_KBL_GT2(dev_priv))
+ i915_perf_unregister_sysfs_kblgt2(dev_priv);
+ else if (IS_KBL_GT3(dev_priv))
+ i915_perf_unregister_sysfs_kblgt3(dev_priv);
+ }
kobject_put(dev_priv->perf.metrics_kobj);
dev_priv->perf.metrics_kobj = NULL;
@@ -3086,6 +3104,16 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
i915_oa_n_builtin_metric_sets_bxt;
dev_priv->perf.oa.ops.select_metric_set =
i915_oa_select_metric_set_bxt;
+ } else if (IS_KBL_GT2(dev_priv)) {
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_kblgt2;
+ dev_priv->perf.oa.ops.select_metric_set =
+ i915_oa_select_metric_set_kblgt2;
+ } else if (IS_KBL_GT3(dev_priv)) {
+ dev_priv->perf.oa.n_builtin_sets =
+ i915_oa_n_builtin_metric_sets_kblgt3;
+ dev_priv->perf.oa.ops.select_metric_set =
+ i915_oa_select_metric_set_kblgt3;
}
}
--
2.11.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
