On Tue, 07 Feb 2017, Ville Syrjälä <ville.syrjala@xxxxxxxxxxxxxxx> wrote:
> On Tue, Feb 07, 2017 at 05:48:46AM -0500, Madhav Chauhan wrote:
>> As per BSPEC, valid cdclk values for glk are 79.2, 158.4, 316.8 Mhz.
>> Practically we can achive only 99% of these cdclk values. So cdclk
>> should be calculated for the given pixclk as per that otherwise it may
>> lead to screen corruption for some scenarios.
>
> I this caused by the hw actually requiring some guardband or simply
> because of our sucky DPLL code not updating the dotclock with the actual
> value the hw is going to produce?
>
> If it's a genuine hw limitation is it documented? And if not has
> someone filed a spec issue for it? And what about other platforms
> (GLK isn't the only one without a guardband in our code after all)?
Indeed. What's the 99% based on? Where is it documented?
BR,
Jani.
>
>>
>> Signed-off-by: Madhav Chauhan <madhav.chauhan@xxxxxxxxx>
>> ---
>> drivers/gpu/drm/i915/intel_display.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 45e5874..2e1bfe9 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -6544,9 +6544,9 @@ static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
>>
>> static int glk_calc_cdclk(int max_pixclk)
>> {
>> - if (max_pixclk > 2 * 158400)
>> + if (max_pixclk > DIV_ROUND_UP(2 * 158400 * 99, 100))
>> return 316800;
>> - else if (max_pixclk > 2 * 79200)
>> + else if (max_pixclk > DIV_ROUND_UP(2 * 79200 * 99, 100))
>> return 158400;
>> else
>> return 79200;
>> --
>> 1.9.1
>>
>> _______________________________________________
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--
Jani Nikula, Intel Open Source Technology Center
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