On Fri, Feb 03, 2017 at 01:58:33PM +0530, Sagar Arun Kamble wrote: > HUC_STATUS, GUC_STATUS, SOFT_SCRATCH registers are read in debugfs > and getparam ioctl. This patch covers those accesses by RPM get/put. > > v2: Covering access in i915_getparam(I915_PARAM_HUC_STATUS) (ChrisW) > > Cc: Arkadiusz Hiler <arkadiusz.hiler@xxxxxxxxx> > Cc: Anusha Srivatsa <anusha.srivatsa@xxxxxxxxx> > Cc: Fiedorowicz, Lukasz <lukasz.fiedorowicz@xxxxxxxxx> > Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 6 ++++++ > drivers/gpu/drm/i915/i915_drv.c | 5 ++--- > 2 files changed, 8 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 3ae0656..639ed12 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -2374,7 +2374,9 @@ static int i915_huc_load_status_info(struct seq_file *m, void *data) > seq_printf(m, "\tRSA: offset is %d; size = %d\n", > huc_fw->rsa_offset, huc_fw->rsa_size); > > + intel_runtime_pm_get(dev_priv); > seq_printf(m, "\nHuC status 0x%08x:\n", I915_READ(HUC_STATUS2)); > + intel_runtime_pm_put(dev_priv); > > return 0; > } Are you sure that HUC_STATUS2 requires RPM get for reading? I remember trying reading it with device forcefully asleep and it succeed just fine. -- Cheers, Arek _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
