== Series Details == Series: Geminilake enabling URL : https://patchwork.freedesktop.org/series/15118/ State : success == Summary == Series 15118v1 Geminilake enabling https://patchwork.freedesktop.org/api/1.0/series/15118/revisions/1/mbox/ fi-bdw-5557u total:244 pass:229 dwarn:0 dfail:0 fail:0 skip:15 fi-bsw-n3050 total:244 pass:204 dwarn:0 dfail:0 fail:0 skip:40 fi-bxt-t5700 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-j1900 total:244 pass:216 dwarn:0 dfail:0 fail:0 skip:28 fi-byt-n2820 total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32 fi-hsw-4770 total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20 fi-hsw-4770r total:244 pass:224 dwarn:0 dfail:0 fail:0 skip:20 fi-ilk-650 total:244 pass:191 dwarn:0 dfail:0 fail:0 skip:53 fi-ivb-3520m total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22 fi-ivb-3770 total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22 fi-kbl-7200u total:244 pass:222 dwarn:0 dfail:0 fail:0 skip:22 fi-skl-6260u total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14 fi-skl-6700hq total:244 pass:223 dwarn:0 dfail:0 fail:0 skip:21 fi-skl-6700k total:244 pass:222 dwarn:1 dfail:0 fail:0 skip:21 fi-skl-6770hq total:244 pass:230 dwarn:0 dfail:0 fail:0 skip:14 fi-snb-2520m total:244 pass:212 dwarn:0 dfail:0 fail:0 skip:32 fi-snb-2600 total:244 pass:211 dwarn:0 dfail:0 fail:0 skip:33 eb88955cdc6a1f4dabff6bc27747c1c9e9a3aaef drm-intel-nightly: 2016y-11m-10d-09h-29m-41s UTC integration manifest e587e04 drm/i915/glk: Configure number of sprite planes properly cc704fe drm/i915/glk: Implement core display init/uninit sequence for geminilake ec6b708 drm/i915/glk: Allow dotclock up to 2 * cdclk on geminilake 0f6ce8d drm/i915/glk: Reuse broxton's cdclk code for GLK 57d0559 drm/i915/glk: Update Port PLL enable sequence for Geminilkae 18ca745 drm/i915/glk: Set DCC delay range 2 in PLL enable sequence 44c1b6b drm/i915/glk: Implement Geminilake DDI init sequence e190020 drm/i915/glk: Add power wells for Geminilake f03db5e drm/i915/glk: Set DDI PHY lane lane optimization for Geminilake too c7815d4 drm/i915/glk: Force DDI initialization. e9db326 drm/i915/glk: Reuse broxton code for geminilake fbd1fe9 drm/i915/glk: Add a IS_GEN9_LP() macro fc0ecef drm/i915/glk: Add Geminilake PCI IDs ba285b3 drm/i915/glk: Introduce Geminilake platform definition fdb5ee2 drm/i915: Create a common GEN9_LP_FEATURE. == Logs == For more details see: https://intel-gfx-ci.01.org/CI/Patchwork_2957/ _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx
