On Mon, Aug 22, 2016 at 10:42:33AM +0200, Maarten Lankhorst wrote:
> On skylake+ the primary plane is plane 0, and plane 1 is the first
> sprite plane. Other callsites handle this correctly.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst@xxxxxxxxxxxxxxx>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 1428d0c1a441..3b1f2c28fbd0 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1325,7 +1325,7 @@ static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
>
> if (INTEL_INFO(dev)->gen >= 9) {
> for_each_sprite(dev_priv, pipe, sprite) {
> - u32 val = I915_READ(PLANE_CTL(pipe, sprite));
> + u32 val = I915_READ(PLANE_CTL(pipe, sprite + 1));
> I915_STATE_WARN(val & PLANE_CTL_ENABLE,
> "plane %d assertion failure, should be off on pipe %c but is still active\n",
> sprite, pipe_name(pipe));
Mind fixing that INTEL_INFO(dev)->gen to INTEL_GEN(dev_priv)
while at it? Obviously it's not introduced by your code, but
it's something that should eventually be fixed anyway, so
while it's in near patch context and doesn't end up causing too
much noise it's nice to get it done piece by piece.
Kind regards, David Weinehall
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