From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Update sysfs and debugfs functions to set SLPC
parameters when setting max/min frequency.
v2: Update for SLPC 2015.2.4 (params for both slice and unslice)
Replace HAS_SLPC with intel_slpc_active() (Paulo)
Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx>
---
drivers/gpu/drm/i915/i915_debugfs.c | 18 ++++++++++++++++++
drivers/gpu/drm/i915/i915_sysfs.c | 18 ++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index a99a3f6..fb497ea1 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -4959,6 +4959,15 @@ i915_max_freq_set(void *data, u64 val)
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
@@ -5015,6 +5024,15 @@ i915_min_freq_set(void *data, u64 val)
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
intel_set_rps(dev_priv, val);
mutex_unlock(&dev_priv->rps.hw_lock);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 8404816..57f9ada 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -408,6 +408,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
dev_priv->rps.max_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MAX_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
@@ -465,6 +474,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
dev_priv->rps.min_freq_softlimit = val;
+ if (intel_slpc_active(dev_priv)) {
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_UNSLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ intel_slpc_set_param(dev_priv,
+ SLPC_PARAM_GLOBAL_MIN_GT_SLICE_FREQ_MHZ,
+ (u32) intel_gpu_freq(dev_priv, val));
+ }
+
val = clamp_t(int, dev_priv->rps.cur_freq,
dev_priv->rps.min_freq_softlimit,
dev_priv->rps.max_freq_softlimit);
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
