From: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> Expose host2guc_action for use by SLPC in intel_slpc.c. Expose functions to allocate and release objects used by GuC to be used for SLPC shared memory object. v5: Updated function names as they need to be made extern. (ChrisW) Signed-off-by: Tom O'Rourke <Tom.O'Rourke@xxxxxxxxx> Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@xxxxxxxxx> --- drivers/gpu/drm/i915/i915_guc_submission.c | 16 ++++++++-------- drivers/gpu/drm/i915/intel_guc.h | 2 ++ 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_guc_submission.c b/drivers/gpu/drm/i915/i915_guc_submission.c index bb40792..680d9b4 100644 --- a/drivers/gpu/drm/i915/i915_guc_submission.c +++ b/drivers/gpu/drm/i915/i915_guc_submission.c @@ -47,7 +47,7 @@ * Firmware writes a success/fail code back to the action register after * processes the request. The kernel driver polls waiting for this update and * then proceeds. - * See host2guc_action() + * See i915_guc_action() * * Doorbells: * Doorbells are interrupts to uKernel. A doorbell is a single cache line (QW) @@ -75,7 +75,7 @@ static inline bool host2guc_action_response(struct drm_i915_private *dev_priv, return GUC2HOST_IS_RESPONSE(val); } -static int host2guc_action(struct intel_guc *guc, u32 *data, u32 len) +int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len) { struct drm_i915_private *dev_priv = guc_to_i915(guc); u32 status; @@ -141,7 +141,7 @@ static int host2guc_allocate_doorbell(struct intel_guc *guc, data[0] = HOST2GUC_ACTION_ALLOCATE_DOORBELL; data[1] = client->ctx_index; - return host2guc_action(guc, data, 2); + return i915_guc_action(guc, data, 2); } static int host2guc_release_doorbell(struct intel_guc *guc, @@ -152,7 +152,7 @@ static int host2guc_release_doorbell(struct intel_guc *guc, data[0] = HOST2GUC_ACTION_DEALLOCATE_DOORBELL; data[1] = client->ctx_index; - return host2guc_action(guc, data, 2); + return i915_guc_action(guc, data, 2); } static int host2guc_sample_forcewake(struct intel_guc *guc, @@ -169,7 +169,7 @@ static int host2guc_sample_forcewake(struct intel_guc *guc, /* bit 0 and 1 are for Render and Media domain separately */ data[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA; - return host2guc_action(guc, data, ARRAY_SIZE(data)); + return i915_guc_action(guc, data, ARRAY_SIZE(data)); } /* @@ -621,7 +621,7 @@ static void i915_guc_submit(struct drm_i915_gem_request *rq) * * Return: A i915_vma if successful, otherwise an ERR_PTR. */ -static struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) +struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size) { struct drm_i915_private *dev_priv = guc_to_i915(guc); struct drm_i915_gem_object *obj; @@ -1066,7 +1066,7 @@ int intel_guc_suspend(struct drm_device *dev) /* first page is shared data with GuC */ data[2] = i915_ggtt_offset(ctx->engine[RCS].state); - return host2guc_action(guc, data, ARRAY_SIZE(data)); + return i915_guc_action(guc, data, ARRAY_SIZE(data)); } @@ -1091,5 +1091,5 @@ int intel_guc_resume(struct drm_device *dev) /* first page is shared data with GuC */ data[2] = i915_ggtt_offset(ctx->engine[RCS].state); - return host2guc_action(guc, data, ARRAY_SIZE(data)); + return i915_guc_action(guc, data, ARRAY_SIZE(data)); } diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index c973262..9e6b948 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -155,9 +155,11 @@ extern int intel_guc_suspend(struct drm_device *dev); extern int intel_guc_resume(struct drm_device *dev); /* i915_guc_submission.c */ +int i915_guc_action(struct intel_guc *guc, u32 *data, u32 len); int i915_guc_submission_init(struct drm_i915_private *dev_priv); int i915_guc_submission_enable(struct drm_i915_private *dev_priv); int i915_guc_wq_check_space(struct drm_i915_gem_request *rq); +struct i915_vma *guc_allocate_vma(struct intel_guc *guc, u32 size); void i915_guc_submission_disable(struct drm_i915_private *dev_priv); void i915_guc_submission_fini(struct drm_i915_private *dev_priv); -- 1.9.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@xxxxxxxxxxxxxxxxxxxxx https://lists.freedesktop.org/mailman/listinfo/intel-gfx