On to, 2016-08-18 at 09:21 +0100, Chris Wilson wrote:
> Only fbc1 is tied to using a fence. Later iterations of fbc are more
> flexible and allow operation on unfenced frontbuffers.
>
> Signed-off-by: Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>
> Cc: Daniel Vetter <daniel.vetter@xxxxxxxxx>
> Cc: "Zanoni, Paulo R" <paulo.r.zanoni@xxxxxxxxx>
I could only find that unfenced compressed framebuffer does not work on
Gen4 but will work Gen6.
So somebody should test with Gen5. Maybe we should document this as a
comment?
Code itself makes sense;
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@xxxxxxxxxxxxxxx>
Regards, Joonas
> ---
> drivers/gpu/drm/i915/intel_fbc.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
> index 57e1ca624d73..9534f90c6551 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -789,8 +789,10 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc)
> */
> if (cache->fb.tiling_mode != I915_TILING_X ||
> cache->fb.fence_reg == I915_FENCE_REG_NONE) {
> - fbc->no_fbc_reason = "framebuffer not tiled or fenced";
> - return false;
> + if (INTEL_GEN(dev_priv) < 5) {
> + fbc->no_fbc_reason = "framebuffer not tiled or fenced";
> + return false;
> + }
> }
> if (INTEL_INFO(dev_priv)->gen <= 4 && !IS_G4X(dev_priv) &&
> cache->plane.rotation != DRM_ROTATE_0) {
--
Joonas Lahtinen
Open Source Technology Center
Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
